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intel corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an intel product. no o ther circuit patent licenses are implied. information contained herein supersedes previously published specifications on these devices from intel . ? intel corporation, 1993 november 199 3 order number: 270727-00 6 80960 c a -33, -25, -1 6 32-bit high-performance embedde d processo r ? two instructions/clock sustained executio n ? four 59 mbytes/s dma channels with data chainin g ? demultiplexed 32-bit burst bus with pipelinin g n 32-bit parallel architectur e ? two instructions/clock executio n ? load/store architectur e ? sixteen 32-bit global register s ? sixteen 32-bit local register s ? manipulates 64-bit bit field s ? 11 addressing mode s ? full parallel fault mode l ? supervisor protection mode l n fast procedure call/return mode l ? full procedure call in 4 clock s n on-chip register cach e ? caches registers on call/re t ? minimum of 6 frames provide d ? up to 15 programmable frame s n on-chip instruction cach e ? 1 kbyte two-way set associativ e ? 128-bit path to instruction sequence r ? cache-lock mode s ? cache-off mod e n high bandwidth on-chip data ra m ? 1 kbyte on-chip data ra m ? sustains 128 bits per clock acces s n four on-chip dma channel s ? 59 mbytes/s fly-by transfer s ? 32 mbytes/s two-cycle transfer s ? data chainin g ? data packing/unpackin g ? programmable priority metho d n 32-bit demultiplexed burst bu s ? 128-bit internal data paths to and from register s ? burst bus for dram interfacin g ? address pipelining optio n ? fully programmable wait state s ? supports 8-, 16- or 32-bit bus width s ? supports unaligned accesse s ? supervisor protection pi n n selectable big or little endian byte orderin g n high-speed interrupt controlle r ? up to 248 external interrupt s ? 32 fully programmable prioritie s ? multi-mode 8-bit interrupt por t ? four internal dma interrupt s ? separate, non-maskable interrupt pi n ? context switch in 750 ns typica l
i i contents pag e 1.0 purpos e ................................................................................................................................ .................. 1 2.0 80960ca overvie w ................................................................................................................................ . 1 2.1 the c-series core .............................................................................................................................. 2 2.2 pipelined, bu r st b us ........................................................................................................................... 2 2.3 flexible dma controller ...................................................................................................................... 2 2.4 priority interrupt controller .................................................................................................................. 2 2.5 instruction set summary .................................................................................................................... 3 3.0 package informatio n ......................................................................................................................... 4 3.1 package introduction .......................................................................................................................... 4 3.2 pin descriptions ................................................................................................................................ .. 4 3.3 80960ca mechanical data ............................................................................................................... 1 1 3.3.1 80960ca pga pinout ............................................................................................................ 1 1 3.3.2 80960ca pqfp pinout .......................................................................................................... 1 5 3.4 package thermal specifications ...................................................................................................... 1 8 3.5 stepping register information .......................................................................................................... 2 0 3.6 suggested sources for 80960ca accessories .................................................................................. 2 0 4.0 electrical specification s ............................................................................................................. 2 1 4.1 absolute maximum ratings .............................................................................................................. 2 1 4.2 operating conditions ........................................................................................................................ 2 1 4.3 recommended connections ............................................................................................................ 2 1 4.4 dc specifications ............................................................................................................................. 2 2 4.5 ac specifications .............................................................................................................................. 2 3 4.5.1 ac test conditions ................................................................................................................ 2 9 4.5.2 ac timing waveforms ........................................................................................................... 2 9 4.5.3 derating curves ..................................................................................................................... 3 3 5.0 reset, backoff and hold acknowledg e ................................................................................. 3 5 6.0 bus waveforms ................................................................................................................................ . 3 6 7.0 revision histor y ................................................................................................................................ 6 4 80960ca-33, -25, -16 32-bit high-performance embedded processo r
ii i contents pag e list of figures figure 1 80960ca block diagram .............................................................................................................. 1 figure 2 80960ca pga pinout?view from top (pins facing down) ...................................................... 1 3 figure 3 80960ca pga pinout ?view from bottom (pins facing up) .................................................... 1 4 figure 4 80960ca pqfp pinout (view from top side) ............................................................................ 1 7 figure 5 measuring 80960ca pga and pqfp case temperature .......................................................... 1 8 figure 6 register g0 ................................................................................................................................ . 2 0 figure 7 ac test load .............................................................................................................................. 2 9 figure 8 input and output clocks waveform ............................................................................................ 2 9 figure 9 clkin waveform ........................................................................................................................ 2 9 figure 10 output delay and float waveform ............................................................................................. 3 0 figure 11 input setup and hold waveform ................................................................................................ 3 0 figure 12 nm i , xint7: 0 input setup and hold waveform .......................................................................... 3 1 figure 13 hold acknowledge timings ........................................................................................................ 3 1 figure 14 bus backoff ( bof f ) timings ...................................................................................................... 3 2 figure 15 relative timings waveforms ...................................................................................................... 3 3 figure 16 output delay or hold vs. load capacitance .............................................................................. 3 3 figure 17 rise and fall time derating at highest operating temperature and minimum v c c .................. 3 4 figure 18 i c c vs. frequency and temperature ........................................................................................... 3 4 figure 19 cold reset waveform ................................................................................................................ 3 6 figure 20 warm reset waveform .............................................................................................................. 3 7 figure 21 entering the once state ........................................................................................................... 3 8 figure 22 clock synchronization in the 2-x clock mode ............................................................................ 3 9 figure 23 clock synchronization in the 1-x clock mode ............................................................................ 3 9 figure 24 non-burst, non-pipelined requests without wait states .......................................................... 4 0 figure 25 non-burst, non-pipelined read request with wait states ....................................................... 4 1 figure 26 non-burst, non-pipelined write request with wait states ....................................................... 4 2 figure 27 burst, non-pipelined read request without wait states, 32-bit bus ........................................ 4 3 figure 28 burst, non-pipelined read request with wait states, 32-bit bus ............................................. 4 4 figure 29 burst, non-pipelined write request without wait states, 32-bit bus ....................................... 4 5 figure 30 burst, non-pipelined write request with wait states, 32-bit bus ............................................. 4 6 figure 31 burst, non-pipelined read request with wait states, 16-bit bus ............................................ 4 7 figure 32 burst, non-pipelined read request with wait states, 8-bit bus ............................................... 4 8 figure 33 non-burst, pipelined read request without wait states, 32-bit bus ....................................... 4 9 figure 34 non-burst, pipelined read request with wait states, 32-bit bus ............................................ 5 0 figure 35 burst, pipelined read request without wait states, 32-bit bus ............................................... 5 1 figure 36 burst, pipelined read request with wait states, 32-bit bus ..................................................... 5 2 figure 37 burst, pipelined read request with wait states, 16-bit bus ..................................................... 5 3 figure 38 burst, pipelined read request with wait states, 8-bit bus ....................................................... 5 4
i v contents pag e list of figure s (continued ) figure 39 using external read y ............................................................................................................... 5 5 figure 40 terminating a burst with bter m ............................................................................................... 5 6 figure 41 bof f functional timing ............................................................................................................ 5 7 figure 42 hold functional timing ............................................................................................................ 5 8 figure 43 dre q and dac k functional timing .......................................................................................... 5 9 figure 44 eo p functional timing .............................................................................................................. 5 9 figure 45 terminal count functional timing .............................................................................................. 6 0 figure 46 fai l functional timing ............................................................................................................... 6 0 figure 47 a summary of aligned and unaligned transfers for little endian regions ................................ 6 1 figure 48 a summary of aligned and unaligned transfers for little endian regions (continued) ............ 6 2 figure 49 idle bus operation ...................................................................................................................... 6 3 list of table s table 1 80960ca instruction set .............................................................................................................. 3 table 2 pin description nomenclature ...................................................................................................... 4 table 3 80960 c a pin description ? external bus signals ...................................................................... 5 table 4 80960ca pin description ? processor control signals .............................................................. 8 table 5 80960 c a pin description ? dma and interrupt unit control signals ....................................... 1 0 table 6 80960ca pga pinout ? in signal order ................................................................................... 1 1 table 7 80960ca pga pinout ? in pin order ........................................................................................ 1 2 table 8 80960ca pqfp pinout ? in signal order ................................................................................. 1 5 table 9 80960ca pqfp pinout ? in pin order ..................................................................................... 1 6 table 10 maximum t a at various airflows in o c (pga package only) ..................................................... 1 8 table 11 80960ca pga package thermal characteristics ...................................................................... 1 9 table 12 80960ca pqfp package thermal characteristics .................................................................... 1 9 table 13 die stepping cross reference ................................................................................................... 2 0 table 14 operating conditions (80960ca-33, -25, -16) ............................................................................ 2 1 table 15 dc characteristics ..................................................................................................................... 2 2 table 16 80960ca ac characteristics (33 mhz) ...................................................................................... 2 3 table 17 80960ca ac characteristics (25 mhz) ...................................................................................... 2 5 table 18 80960ca ac characteristics (16 mhz) ...................................................................................... 2 7 table 19 reset conditions ........................................................................................................................ 3 5 table 20 hold acknowledge and backoff conditions ................................................................................ 3 5
1 80960ca-33, -25, -1 6 1.0 purpos e this document provides electrical characteristics for the 33, 25 and 16 mhz versions of the 80960c a . for a detailed description of any 80960 c a functional topic?other than parametric performance?consult the 80960ca product overview (order no. 270669) or the i96 0 ca microprocessor user?s manual (order no. 270710 ) . to obtain data sheet updates and errata, please call intel?s faxbac k data-on- demand system (1-800-628-2283 or 916-356-3105). other information can be obtained from intel?s tec h - nical bbs (916-356-3600) . 2.0 80960 c a overvie w the 80960ca is the second-generation member of the 80960 family of embedded processors . the 80960 c a is object code compatible with the 32-bit 80960 core architecture while including special function register extensions to control on-chip peripherals and instruction set extensions to shift 64- bit operands and configure on-chip hardware. multiple 128-bit internal buses, on-chip instruction caching and a sophisticated instruction scheduler allow the processor to sustain execution of two instructions every clock and peak at execution of three instructions per clock . a 32-bit demultiplexed and pipelined burst bus provides a 13 2 mbyte/s bandwidth to a system?s high-speed external memory sub-system. in addition, the 80960 c a ?s on-chip caching of instru c - tions, procedure context and critical program data substantially decouple system performance from the wait states associated with accesses to the system?s slower, cost sensitive, main memory subsystem . the 80960 c a bus controller integrates full wait state and bus width control for highest system perfo r - mance with minimal system design complexity. unaligned access and big endian byte order support reduces the cost of porting existing applications to the 80960 c a . the processor also integrates four complete data- chaining dma channels and a high-speed interrupt controller on-chip. dma channels perform: single- cycle or two-cycle transfers, data packing and unpacking and data chaining. block transfers?in addition to source or destination synchronized tran s - fers?are provided . the interrupt controller provides full programmability of 248 interrupt sources into 32 priority levels with a typical interrupt task switch (?latency?) time of 75 0 ns . figure 1. 80960 c a block diagra m execution unit programmable bu s controller bus request queues six-port register file 64-bit src1 bus 64-bit src2 bus 64-bit dst bus 32-bit base bus 128-bit load bus 128-bit store bus instruction prefetch queue instruction cache (1 kbyte, two-way set associative) 128-bit cache bus interrupt controller control address data memory-side machine bus register-side machine bus parallel instruction schedule r memory region configuration multiply/divide unit four-channel dma controller interrupt port 1 kbyte 5 to 15 sets register cache data ram address generation unit f_cx001a dma port
2 80960ca-33, -25, -1 6 2.1 the c-series cor e the c-series core is a very high performance microarchitectural implementation of the 80960 core architecture. the c-series core can sustain exec u - tion of two instructions per clock (6 6 mips at 3 3 mhz). to achieve this level of performance, intel has incorporated state-of-the-art silicon technology and innovative microarchitectural constructs into the implementation of the c-series core. factors that contribute to the core?s performance include : ? parallel instruction decoding allows issuance of up to three instructions per cloc k ? single-clock execution of most instructions ? parallel instruction decode allows sustained, simultaneous execution of two single-clock instructions every clock cycl e ? efficient instruction pipeline minimizes pipeline break losse s ? register and resource scoreboarding allow simu l - taneous multi-clock instruction executio n ? branch look-ahead and prediction allows many branches to execute with no pipeline brea k ? local register cache integrated on-chip caches call/return contex t ? two-way set associative, 1 kbyte integrated instruction cach e ? 1 kbyte integrated data ram sustains a four- word (128-bit) access every clock cycl e 2.2 pipelined, burst bu s a 32-bit high performance bus controller interfaces the 80960 c a to external memory and peripherals. the bus control unit features a maximum transfer rate of 13 2 mbytes per second (at 3 3 mhz). inte r - nally programmable wait states and 16 separately configurable memory regions allow the processor to interface with a variety of memory subsystems with a minimum of system complexity and a maximum of performance. the bus controller?s main features include : ? demultiplexed, burst bus to exploit most efficient dram access mode s ? address pipelining to reduce memory cost while maintaining performanc e ? 32-, 16- and 8-bit modes for i/o interfacing eas e ? full internal wait state generation to reduce system cos t ? little and big endian support to ease application developmen t ? unaligned access support for code portabilit y ? three-deep request queue to decouple the bus from the cor e 2.3 flexible dma controlle r a four-channel dma controller provides high speed dma control for data transfers involving peripherals and memory. the dma provides advanced features such as data chaining, byte assembly and disa s - sembly and a high performance fly-by mode capable of transfer speeds of up to 5 9 mbytes per second at 3 3 mhz. the dma controller features a performance and flexibility which is only possible by integrating the dma controller and the 80960 c a core . 2.4 priority interrupt controlle r a programmable-priority interrupt controller manages up to 248 external sources through the 8- bit external interrupt port. the interrupt unit also handles the four internal sources from the dma controller and a single non-maskable interrupt input. the 8-bit interrupt port can also be configured to provide individual interrupt sources that are level or edge triggered . interrupts in the 80960 c a are prioritized and signaled within 27 0 ns of the request. if the interrupt is of higher priority than the processor priority, the context switch to the interrupt routine typically is complete in another 48 0 ns. the interrupt unit provides the mechanism for the low latency and high throughput interrupt service which is essential for embedded applications .
3 80960ca-33, -25, -1 6 2.5 instruction set summar y table 1 summarizes the 80960 c a instruction set by logical groupings. see the i96 0 ca microprocessor user?s manual for a complete description of the instruction set . table 1. 80960 c a instruction se t data movemen t arithmeti c logica l bit and bit field and byt e loa d stor e mov e load addres s ad d subtrac t multipl y divid e remainde r modul o shif t *extended shif t extended multipl y extended divid e add with carr y subtract with carr y rotat e an d not an d and no t o r exclusive o r not o r or no t no r exclusive no r no t nan d set bi t clear bi t not bi t alter bi t scan for bi t span over bi t extrac t modif y scan byte for equa l compariso n branc h call/retur n faul t compar e conditional compar e compare and incremen t compare and decremen t test condition cod e check bi t unconditional branc h conditional branc h compare and branc h cal l call extende d call syste m retur n branch and lin k conditional faul t synchronize fault s debu g processor managemen t atomi c modify trace control s mar k force mar k flush local register s modify arithmetic control s modify process control s *system contro l *dma contro l atomic ad d atomic modif y notes : instructions marked by (*) are 80960 c a extensions to the 80960 instruction set .
4 80960ca-33, -25, -1 6 3.0 package informatio n 3.1 package introductio n this section describes the pins, pinouts and thermal characteristics for the 80960 c a in the 168-pin ceramic pin grid array (pga) package and the 196- pin plastic quad flat package (pqfp). for complete package specifications and information, see the packaging handbook (order no. 240800) . 3.2 pin description s the 80960 c a pins are described in this section. table 2 presents the legend for interpreting the pin descriptions in the following tables. pins associated with the 32-bit demultiplexed processor bus are described in table 3 . pins associated with basic processor configuration and control are described in table 4 . pins associated with the 80960 c a dma controller and interrupt unit are described in table 5 . all pins float while the processor is in the once mode . table 2. pin description nomenclatur e symbo l descriptio n i input only pi n o output only pi n i/ o pin can be either an input or outpu t ? pins ?must be? connected as describe d s(... ) synchronous. inputs must meet setup and hold times relative to pclk2:1 for proper operation. all outputs are synchronous to pclk2:1. s(e) edge sensitive input s(l) level sensitive inpu t a(... ) asynchronous. inputs may be asynchronous to pclk2:1. a(e) edge sensitive input a(l) level sensitive inpu t h(... ) while the processor?s bus is in the hold acknowledge or bus backoff state, the pin: h(1) is driven to v cc h(0) is driven to v ss h(z) floats h(q) continues to be a valid inpu t r(... ) while the processor?s rese t pin is low, the pin: r(1) is driven to v cc r(0) is driven to v ss r(z) floats r(q) continues to be a valid outpu t
5 80960ca-33, -25, -1 6 table 3. 80960 c a pin description ? external bus signal s (sheet 1 of 3 ) nam e typ e descriptio n a31: 2 o s h(z) r(z ) address bu s carries the physical address? upper 30 bits. a31 is the most significant address bit; a2 is the least significant. during a bus access, a31:2 identify all external addresses to word (4-byte) boundaries. the byte enable signals indicate the selected byte in each word. during burst accesses, a3:2 increment to indicate successive data cycles . d31: 0 i/o s(l) h(z) r(z ) data bus carries 32-, 16- or 8-bit data quantities depending on bus width config u - ration. the least significant bit of the data is carried on d0 and the most significant on d31. when the bus is configured for 8-bit data, the lower 8 data lines, d7:0 are used. for 16-bit data bus widths, d15:0 are used. for 32-bit bus widths the full data bus is used . be3: 0 o s h(z) r(1 ) byte enable s select which of the four bytes addressed by a31:2 are active during an access to a memory region configured for a 32-bit data-bus width. be 3 applies to d31:24; be 2 applies to d23:16; be 1 applies to d15:8 be 0 applies to d7:0 . 32-bit bus: be 3 ?byte enable 3 ?enable d31:2 4 be 2 ?byte enable 2 ?enable d23:1 6 be 1 ?byte enable 1 ?enable d15: 8 be 0 ?byte enable 0 ?enable d7: 0 for accesses to a memory region configured for a 16-bit data-bus width, the processor uses the be 3 , be 1 and be 0 pins as bh e , a1 and bl e respectively . 16-bit bus: be 3 ?byte high enable ( bh e ) ?enable d15: 8 be 2 ?not used (driven high or low ) be 1 ?address bit 1 (a1 ) be 0 ?byte low enable ( bl e ) ?enable d7: 0 for accesses to a memory region configured for an 8-bit data-bus width, the processor uses the be 1 and be 0 pins as a1 and a0 respectively . 8-bit bus: be 3 ?not used (driven high or low ) be 2 ?not used (driven high or low ) be 1 ?address bit 1 (a1 ) be 0 ?address bit 0 (a0 ) w / r o s h(z) r(0 ) write/rea d is asserted for read requests and deasserted for write requests. the w / r signal changes in the same clock cycle as ad s . it remains valid for the entire access in non-pipelined regions. in pipelined regions, w / r is not guaranteed to be valid in the last cycle of a read access . ad s o s h(z) r(1 ) address strob e indicates a valid address and the start of a new bus access. ad s is asserted for the first clock of a bus access .
6 80960ca-33, -25, -1 6 read y i s(l) h(z) r(z ) read y is an input which signals the termination of a data transfer. read y is used to indicate that read data on the bus is valid or that a write-data transfer has completed. the read y signal works in conjunction with the internally programmed wait-state generator. if read y is enabled in a region, the pin is sampled after the programmed number of wait-states has expired. if the read y pin is deasserted, wait states continue to be inserted until read y becomes asserted. this is true for the n ra d , n rd d , n wa d and n wd d wait states. the n xd a wait states cannot be extended . bter m i s(l) h(z) r(z ) burst terminat e is an input which breaks up a burst access and causes another address cycle to occur. the bter m signal works in conjunction with the internally programmed wait-state generator. if read y and bter m are enabled in a region, the bter m pin is sampled after the programmed number of wait states has expired. when bter m is asserted, a new ad s signal is generated and the access is completed. the read y input is ignored when bter m is asserted. bter m must be externally synchronized to satisfy bter m setup and hold times . wai t o s h(z) r(1 ) wai t indicates internal wait state generator status. wai t is asserted when wait states are being caused by the internal wait state generator and not by the read y or bter m inputs. wai t can be used to derive a write-data strobe. wai t can also be thought of as a read y output that the processor provides when it is inserting wait states . blas t o s h(z) r(0 ) burst las t indicates the last transfer in a bus access. blas t is asserted in the last data transfer of burst and non-burst accesses after the wait state counter reaches zero. blas t remains asserted until the clock following the last cycle of the last data transfer of a bus access. if the read y or bter m input is used to extend wait states, the blas t signal remains asserted until read y or bter m terminates the access . dt / r o s h(z) r(0 ) data transmit/receiv e indicates direction for data transceivers. dt / r is used in conjunction with de n to provide control for data transceivers attached to the external bus. when dt / r is asserted, the signal indicates that the processor receives data. conversely, when deasserted, the processor sends data. dt / r changes only while de n is high . de n o s h(z) r(1 ) data enabl e indicates data cycles in a bus request. de n is asserted at the start of the bus request first data cycle and is deasserted at the end of the last data cycle. de n is used in conjunction with dt / r to provide control for data transceivers attached to the external bus. de n remains asserted for sequential reads from pipelined memory regions. de n is deasserted when dt / r changes . loc k o s h(z) r(1 ) bus loc k indicates that an atomic read-modify-write operation is in progress. loc k may be used to prevent external agents from accessing memory which is currently involved in an atomic operation. loc k is asserted in the first clock of an atomic operation and deasserted in the clock cycle following the last bus access for the atomic operation. to allow the most flexibility for memory system enforcement of locked accesses, the processor acknowledges a bus hold request when loc k is asserted. the processor performs dma transfers while loc k is active . hol d i s(l) h(z) r(z ) hold reques t signals that an external agent requests access to the external bus. the processor asserts holda after completing the current bus request. hold, holda and breq are used together to arbitrate access to the processor?s external bus by external bus agents . table 3. 80960 c a pin description ? external bus signal s (sheet 2 of 3 ) nam e typ e descriptio n
7 80960ca-33, -25, -1 6 bof f i s(l) h(z) r(z ) bus backof f , when asserted, suspends the current access and causes the bus pins to float. when bof f is deasserted, the ad s signal is asserted on the next clock cycle and the access is resumed . hold a o s h(1) r(q ) hold acknowledg e indicates to a bus requestor that the processor has reli n - quished control of the external bus. when holda is asserted, the external address bus, data bus and bus control signals are floated. hold, bof f , holda and breq are used together to arbitrate access to the processor?s external bus by external bus agents. since the processor grants hold requests and enters the hold acknowledge state even while rese t is asserted, the state of the holda pin is independent of the rese t pin . bre q o s h(q) r(0 ) bus reques t is asserted when the bus controller has a request pending. breq can be used by external bus arbitration logic in conjunction with hold and holda to determine when to return mastership of the external bus to the processor . d / c o s h(z) r(z ) data or cod e is asserted for a data request and deasserted for instruction requests. d / c has the same timing as w / r . dm a o s h(z) r(z ) dma acces s indicates whether the bus request was initiated by the dma controller. dm a is asserted for any dma request. dm a is deasserted for all other requests . su p o s h(z) r(z ) supervisor acces s indicates whether the bus request is issued while in supervisor mode. su p is asserted when the request has supervisor privileges and is deasserted otherwise. su p can be used to isolate supervisor code and data structures from non-supervisor requests . table 3. 80960 c a pin description ? external bus signal s (sheet 3 of 3 ) nam e typ e descriptio n
8 80960ca-33, -25, -1 6 table 4. 80960 c a pin description ? processor control signals (sheet 1 of 2 ) nam e typ e descriptio n rese t i a(l) h(z) r(z) rese t causes the chip to reset. when rese t is asserted, all external signals return to the reset state. when rese t is deasserted, initialization begins. when the 2-x clock mode is selected, rese t must remain asserted for 32 clkin cycles before being deasserted to guarantee correct processor initialization. when the 1-x clock mode is selected, rese t must remain asserted for 10,000 clkin cycles before being deasserted to guarantee correct processor initialization. the clkmode pin selects 1-x or 2-x input clock division of the clkin pin . the processor?s hold acknowledge bus state functions while the chip is reset. if the processor?s bus is in the hold acknowledge state when rese t is asserted, the processor will internally reset, but maintains the hold acknowledge state on external pins until the hold request is removed. if a hold request is made while the processor is in the reset state, the processor bus will grant holda and enter the hold acknowledge state . fai l o s h(q) r(0) fai l indicates failure of the processor?s self-test performed at initialization. when rese t is deasserted and the processor begins initialization, the fai l pin is asserted. an internal self-test is performed as part of the initialization process. if this self-test passes, the fai l pin is deasserted; otherwise it remains asserted. the fai l pin is reasserted while the processor performs an external bus self-confidence test. if this self-test passes, the processor deasserts the fai l pin and branches to the user?s initialization routine; otherwise the fai l pin remains asserted. internal self-test and the use of the fai l pin can be disabled with the stest pin . stes t i s(l) h(z) r(z ) self test causes the processor?s internal self-test feature to be enabled or disabled at initialization. stest is read on the rising edge of rese t . when asserted, the processor?s internal self-test and external bus confidence tests are performed during processor initialization. when deasserted, only the bus confidence tests are performed during initialization . onc e i a(l) h(z) r(z ) on circuit emulatio n , when asserted, causes all outputs to be floated. onc e is continuously sampled while rese t is low and is latched on the rising edge of rese t . to place the processor in the once state : (1) assert rese t and onc e (order does not matter ) (2) wait for at least 16 clkin periods in 2-x mode?or 10,000 clkin periods in 1-x mode?after v c c and clkin are within operating specification s (3) deassert rese t (4) wait at least 32 clkin period s (the processor will now be latched in the once state as long as rese t is high. ) to exit the once state, bring v c c and clkin to operating conditions, then assert rese t and bring onc e high prior to deasserting rese t . clkin must operate within the specified operating conditions of the processor until step 4 above has been completed. clkin may then be changed to dc to achieve the lowest possible once mode leakage current . onc e can be used by emulator products or for board testers to effectively make an installed processor transparent in the board .
9 80960ca-33, -25, -1 6 clki n i a(e) h(z) r(z ) clock inpu t is an input for the external clock needed to run the processor. the external clock is internally divided as prescribed by the clkmode pin to produce pclk2:1 . clkmod e i a(l) h(z) r(z ) clock mod e selects the division factor applied to the external clock input (clkin). when clkmode is high, clkin is divided by one to create pclk2:1 and the processor?s internal clock. when clkmode is low, clkin is divided by two to create pclk2:1 and the processor?s internal clock. clkmode should be tied high or low in a system as the clock mode is not latched by the processor. if left unconnected, the processor will internally pull the clkmode pin low, enabling the 2-x clock mode . pclk2: 1 o s h(q) r(q ) processor output clock s provide a timing reference for all processor inputs and outputs. all input and output timings are specified in relation to pclk2 and pclk1. pclk2 and pclk1 are identical signals. two output pins are provided to allow flexibility in the system?s allocation of capacitive loading on the clock. pclk2:1 may also be connected at the processor to form a single clock signal . v s s ? groun d connections must be connected externally to a v s s board plane . v c c ? powe r connections must be connected externally to a v c c board plane . v ccpl l ? v ccpl l is a separate v c c supply pin for the phase lock loop used in 1-x clock mode. connecting a simple lowpass filter to v ccpl l may help reduce clock jitter ( t c p ) in noisy environments. otherwise, v ccpl l should be connected to v c c . this pin is implemented starting with the d-stepping. see table 1 3 for die stepping information . n c ? no connec t pins must not be connected in a system . table 4. 80960 c a pin description ? processor control signals (sheet 2 of 2 ) nam e typ e descriptio n
1 0 80960ca-33, -25, -1 6 table 5. 80960 c a pin description ? dma and interrupt unit control signals nam e typ e descriptio n dreq3: 0 i a(l) h(z) r(z ) dma reques t causes a dma transfer to be requested. each of the four signals requests a transfer on a single channel. dreq 0 requests channel 0, dreq 1 requests channel 1, etc. when two or more channels are requested simult a - neously, the channel with the highest priority is serviced first. the channel priority mode is programmable . dack3: 0 o s h(1) r(1 ) dma acknowledg e indicates that a dma transfer is being executed. each of the four signals acknowledges a transfer for a single channel. dack 0 acknow l - edges channel 0, dack 1 acknowledges channel 1, etc. dack3: 0 are asserted when the requesting device of a dma is accessed . eo p / tc3: 0 i/o a(l) h(z/q) r(z ) end of process/terminal coun t can be programmed as either an input ( eop3: 0 ) or as an output ( tc3: 0 ), but not both. each pin is individually progra m - mable. when programmed as an input, eop x causes the termination of a current dma transfer for the channel corresponding to the eop x pin. eop 0 corresponds to channel 0, eop 1 corresponds to channel 1, etc. when a channel is configured for source an d destination chaining, the eop pin for that channel causes termination of only the current buffer transferred and causes the next buffer to be transferred. eop3: 0 are asynchronous inputs . when programmed as an output, the channel?s tc x pin indicates that the channel byte count has reached 0 and a dma has terminated. tc x is driven with the same timing as dack x during the last dma transfer for a buffer. if the last bus request is executed as multiple bus accesses, tc x will stay asserted for the entire bus request . xint7: 0 i a(e/l) h(z) r(z ) external interrupt pin s cause interrupts to be requested. these pins can be configured in three modes : dedicated mode : each pin is a dedicated external interrupt source. dedicated inputs can be individually programmed to be level (low) or edge (falling) activated. expanded mode : the eight pins act together as an 8-bit vectored interrupt source. the interrupt pins in this mode are level activa t - ed.since the interrupt pins are active low, the vector number requested is the one?s complement of the positive logic value place on the port. this eliminates glue logic to interface to combinational priority encoders which output negative logic . mixed mode : xint7: 5 are dedicated sources and xint4: 0 act as the five most significant bits of an expanded mode vector. the least significant bits are set to 010 internally . nm i i a(e) h(z) r(z ) non-maskable interrup t causes a non-maskable interrupt event to occur. nm i is the highest priority interrupt recognized. nm i is an edge (falling) activated source .
1 1 80960ca-33, -25, -1 6 3.3 80960 c a mechanical dat a 3.3.1 80960 c a pga pinou t tables 6 and 7 list the 80960 c a pin names with package location. figure 2 depicts the complete 80960 c a pga pinout as viewed from the top side of the component (i.e., pins facing down). figure 3 shows the complete 80960 c a pga pinout as viewed from the pin-side of the package (i.e., pins facing up). see section 4.0, electrical specification s for specifications and recommended connections . table 6. 80960 c a pga pinout ? in signal orde r address bu s data bu s bus contro l processor contro l i/ o signa l pi n signa l pi n signa l pi n signa l pi n signa l pi n a3 1 s1 5 d3 1 r 3 be 3 s 5 rese t a1 6 dreq 3 a 7 a3 0 q1 3 d3 0 q 5 be 2 s 6 dreq 2 b 6 a2 9 r1 4 d2 9 s 2 be 1 s 7 fai l a 2 dreq 1 a 6 a2 8 q1 4 d2 8 q 4 be 0 r 9 dreq 0 b 5 a2 7 s1 6 d2 7 r 2 stes t b 2 a2 6 r1 5 d2 6 q 3 w / r s1 0 dack 3 a1 0 a2 5 s1 7 d2 5 s 1 onc e c 3 dack 2 a 9 a2 4 q1 5 d2 4 r 1 ad s r 6 dack 1 a 8 a2 3 r1 6 d2 3 q 2 clki n c1 3 dack 0 b 8 a2 2 r1 7 d2 2 p 3 read y s 3 clkmod e c1 4 a2 1 q1 6 d2 1 q 1 bter m r 4 plck 1 b1 4 eo p / tc 3 a1 4 a2 0 p1 5 d2 0 p 2 plck 2 b1 3 eo p / tc 2 a1 3 a1 9 p1 6 d1 9 p 1 wai t s1 2 eo p / tc 1 a1 2 a1 8 q1 7 d1 8 n 2 blas t s 8 v s s eo p / tc 0 a1 1 a1 7 p1 7 d1 7 n 1 locatio n a1 6 n1 6 d1 6 m 1 dt / r s1 1 c7, c8, c9, c10, c11, c12, f15, g3, g15, h3, h15, j3, j15, k3, k15, l3, l15, m3, m15, q7, q8, q9, q10, q1 1 xint 7 c1 7 a1 5 n1 7 d1 5 l 1 de n s 9 xint 6 c1 6 a1 4 m1 7 d1 4 l 2 xint 5 b1 7 a1 3 l1 6 d1 3 k 1 loc k s1 4 xint 4 c1 5 a1 2 l1 7 d1 2 j 1 xint 3 b1 6 a1 1 k1 7 d1 1 h 1 v c c xint 2 a1 7 a1 0 j1 7 d1 0 h 2 hol d r 5 locatio n xint 1 a1 5 a 9 h1 7 d 9 g 1 hold a s 4 b7, b9, b11, b12, c6, e15, f3, f16, g2, h16, j2, j16, k2, k16, m2, m16, n3, n15, q6, r7, r8, r10, r1 1 xint 0 b1 5 a 8 g1 7 d 8 f 1 bre q r1 3 a 7 g1 6 d 7 e 1 nm i d1 5 a 6 f1 7 d 6 f 2 d / c s1 3 a 5 e1 7 d 5 d 1 dm a r1 2 a 4 e1 6 d 4 e 2 su p q1 2 v ccpl l b1 0 a 3 d1 7 d 3 c 1 no connec t a 2 d1 6 d 2 d 2 bof f b 1 locatio n d 1 c 2 a1, a3, a4, a5, b3, b4, c4, c5, d 3 d 0 e 3
1 2 80960ca-33, -25, -1 6 table 7. 80960 c a pga pinout ? in pin orde r pi n signa l pi n signa l pi n signa l pi n signa l pi n signa l a 1 n c c 1 d 3 g 1 d 9 m 1 d1 6 r 1 d2 4 a 2 fai l c 2 d 1 g 2 v c c m 2 v c c r 2 d2 7 a 3 n c c 3 onc e g 3 v s s m 3 v s s r 3 d3 1 a 4 n c c 4 n c g1 5 v s s m1 5 v s s r 4 bter m a 5 n c c 5 n c g1 6 a 7 m1 6 v c c r 5 hol d a 6 dreq 1 c 6 v c c g1 7 a 8 m1 7 a1 4 r 6 ad s a 7 dreq 3 c 7 v s s r 7 v c c a 8 dack 1 c 8 v s s h 1 d1 1 n 1 d1 7 r 8 v c c a 9 dack 2 c 9 v s s h 2 d1 0 n 2 d1 8 r 9 be 0 a1 0 dack 3 c1 0 v s s h 3 v s s n 3 v c c r1 0 v c c a1 1 eo p / tc 0 c1 1 v s s h1 5 v s s n1 5 v c c r1 1 v c c a1 2 eo p / tc 1 c1 2 v s s h1 6 v c c n1 6 a1 6 r1 2 dm a a1 3 eo p / tc 2 c1 3 clki n h1 7 a 9 n1 7 a1 5 r1 3 bre q a1 4 eo p / tc 3 c1 4 clkmod e r1 4 a2 9 a1 5 xint 1 c1 5 xint 4 j 1 d1 2 p 1 d1 9 r1 5 a2 6 a1 6 rese t c1 6 xint 6 j 2 v c c p 2 d2 0 r1 6 a2 3 a1 7 xint 2 c1 7 xint 7 j 3 v s s p 3 d2 2 r1 7 a2 2 j1 5 v s s p1 5 a2 0 b 1 bof f d 1 d 5 j1 6 v c c p1 6 a1 9 s 1 d2 5 b 2 stes t d 2 d 2 j1 7 a1 0 p1 7 a1 7 s 2 d2 9 b 3 n c d 3 n c s 3 read y b 4 n c d1 5 nm i k 1 d1 3 q 1 d2 1 s 4 hold a b 5 dreq 0 d1 6 a 2 k 2 v c c q 2 d2 3 s 5 be 3 b 6 dreq 2 d1 7 a 3 k 3 v s s q 3 d2 6 s 6 be 2 b 7 v c c k1 5 v s s q 4 d2 8 s 7 be 1 b 8 dack 0 e 1 d 7 k1 6 v c c q 5 d3 0 s 8 blas t b 9 v c c e 2 d 4 k1 7 a1 1 q 6 v c c s 9 de n b1 0 v ccpl l e 3 d 0 q 7 v s s s1 0 w / r b1 1 v c c e1 5 v c c l 1 d1 5 q 8 v s s s1 1 dt / r b1 2 v c c e1 6 a 4 l 2 d1 4 q 9 v s s s1 2 wai t b1 3 pclk 2 e1 7 a 5 l 3 v s s q1 0 v s s s1 3 d / c b1 4 pclk 1 l1 5 v s s q1 1 v s s s1 4 loc k b1 5 xint 0 f 1 d 8 l1 6 a1 3 q1 2 su p s1 5 a3 1 b1 6 xint 3 f 2 d 6 l1 7 a1 2 q1 3 a3 0 s1 6 a2 7 b1 7 xint 5 f 3 v c c q1 4 a2 8 s1 7 a2 5 f1 5 v s s q1 5 a2 4 f1 6 v c c q1 6 a2 1 f1 7 a 6 q1 7 a1 8
1 3 80960ca-33, -25, -1 6 figure 2. 80960 c a pga pinout ? view from top (pins facing down ) d5 d7 d8 d9 d11 d12 d13 d15 d16 d17 d19 d21 d24 d25 d2 d4 d6 v cc d10 v cc v cc d14 v cc d18 d20 d23 d27 d29 nc d0 v cc v ss v ss v ss v ss v ss v ss v cc d22 d31 ready d26 d28 bterm holda d30 hold be3 v cc ads be2 v ss v cc be1 v ss v cc blast v ss be0 den v ss v cc w / r v ss v cc dt / r a29 lock sup wait dma a28 a30 breq d / c d3 d1 once nc nc v cc v ss v ss v ss v ss v ss clkin clk mode v ss boff stest nc nc dreq0 dreq2 v cc dack0 v c c v ccpll v cc pclk2 pclk1 v cc nc fail nc nc nc dreq1 dreq3 dack1 dack2 dack3 eo p / tc0 eo p / tc2 eo p / tc3 eo p / tc1 v ss a2 v cc a22 a25 a20 v ss a3 a5 nmi v cc v ss v ss v ss v ss v ss a24 a31 a26 a4 v cc a6 a8 a9 a10 a11 a12 a14 a15 a17 a18 v cc v cc v cc a13 v cc a16 a19 a21 a23 a27 a7 xint6 xint7 xint4 xint3 xint5 xint0 reset xint2 xint1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a b c d e f g h j k l m n p q r s f_ca002a a b c d e f g h j k l m n p q r s
1 4 80960ca-33, -25, -1 6 figure 3. 80960 c a pga pinout ? view from bottom (pins facing up ) d5 d7 d8 d9 d11 d12 d13 d15 d16 d17 d19 d21 d24 d25 d2 d4 d6 v cc d10 v cc v cc d14 v cc d18 d20 d23 d27 d29 nc d0 v cc v ss v ss v ss v ss v ss v ss v cc d22 d31 ready d26 d28 bterm holda d30 hold be3 v cc ads be2 v ss v cc be1 v ss v cc blast v ss be0 den v ss v cc w / r v ss v cc dt / r a29 lock sup wait dma a28 a30 breq d / c d3 d1 once nc nc v cc v ss v ss v ss v ss v ss clkin clk mode v ss boff stest nc nc dreq0 dreq2 v cc dack0 v c c v ccpll v cc pclk2 pclk1 v cc nc fail nc nc nc dreq1 dreq3 dack1 dack2 dack3 eo p / tc0 eo p / tc2 eo p / tc3 eo p / tc1 v ss a2 v cc a22 a25 a20 v ss a3 a5 nmi v cc v ss v ss v ss v ss v ss a24 a31 a26 a4 v cc a6 a8 a9 a10 a11 a12 a14 a15 a17 a18 v cc v cc v cc a13 v cc a16 a19 a21 a23 a27 a7 xint6 xint7 xint4 xint3 xint5 xint0 reset xint2 xint1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 f_ca003a a b c d e f g h j k l m n p q r s a b c d e f g h j k l m n p q r s metal lid
1 5 80960ca-33, -25, -1 6 3.3.2 80960 c a pqfp pinou t tables 8 and 9 list the 80960 c a pin names with package location. figure 4 shows the 80960 c a pqfp pinout as viewed from the top side . see section 4.0, electrical specification s for specifications and recommended connections . table 8. 80960 c a pqfp pinout ? in signal orde r address bu s data bu s bus contro l processor contro l i/ o signa l pi n signa l pi n signa l pi n signa l pi n signa l pi n a3 1 15 3 d3 1 18 6 be 3 17 6 rese t 9 1 dreq 3 6 0 a3 0 15 2 d3 0 18 7 be 2 17 5 fai l 4 5 dreq 2 5 9 a2 9 15 1 d2 9 18 8 be 1 17 2 stes t 4 6 dreq 1 5 8 a2 8 14 5 d2 8 18 9 be 0 17 0 onc e 4 3 dreq 0 5 7 a2 7 14 4 d2 7 19 1 clki n 8 7 a2 6 14 3 d2 6 19 2 w / r 16 4 clkmod e 8 5 dack 3 6 5 a2 5 14 2 d2 5 19 4 pclk 2 7 4 dack 2 6 4 a2 4 14 1 d2 4 19 5 ad s 17 8 pclk 1 7 8 dack 1 6 3 a2 3 13 9 d2 3 3 v s s dack 0 6 2 a2 2 13 8 d2 2 4 read y 18 2 locatio n a2 1 13 7 d2 1 5 bter m 18 4 2, 7, 16, 24, 30, 38, 39, 49, 56, 70, 75, 77, 81, 83, 88, 89, 92, 98, 105, 109, 110, 121, 125, 131, 135, 147, 150, 161, 165, 173, 174, 185, 19 6 eo p / tc 3 6 9 a2 0 13 6 d2 0 6 eo p / tc 2 6 8 a1 9 13 4 d1 9 8 wai t 16 2 eo p / tc 1 6 7 a1 8 13 3 d1 8 9 blas t 16 9 eo p / tc 0 6 6 a1 7 13 2 d1 7 1 0 a1 6 13 0 d1 6 1 1 dt / r 16 3 xint 7 10 7 a1 5 12 9 d1 5 1 3 de n 16 7 v c c xint 6 10 6 a1 4 12 8 d1 4 1 4 locatio n xint 5 10 2 a1 3 12 4 d1 3 1 5 loc k 15 6 1, 12, 20, 28, 32, 37, 44, 50, 61, 71, 79, 82, 96, 99, 103, 115, 127, 140, 148, 154, 168, 171, 180, 19 0 xint 4 10 1 a1 2 12 3 d1 2 1 7 xint 3 10 0 a1 1 12 2 d1 1 1 8 hol d 18 1 xint 2 9 5 a1 0 12 0 d1 0 1 9 hold a 17 9 xint 1 9 4 a 9 11 9 d 9 2 1 bre q 15 5 xint 0 9 3 a 8 11 8 d 8 2 2 v ccpl l 7 2 a 7 11 7 d 7 2 3 d / c 15 9 no connec t nm i 10 8 a 6 11 6 d 6 2 5 dm a 16 0 locatio n a 5 11 4 d 5 2 6 su p 15 8 29, 31, 41, 42, 47, 48, 51, 52, 53, 54, 55, 73, 76, 80, 84, 86, 90, 97, 104, 126, 146, 149, 157, 166, 177, 183, 19 3 a 4 11 3 d 4 2 7 a 3 11 2 d 3 3 3 bof f 4 0 a 2 11 1 d 2 3 4 d 1 3 5 d 0 3 6
1 6 80960ca-33, -25, -1 6 table 9. 80960 c a pqfp pinout ? in pin orde r pi n signa l pi n signa l pi n signa l pi n signa l pi n signa l pi n signa l 1 v c c 3 4 d 2 6 7 eo p / tc 1 10 0 xint 3 13 3 a1 8 16 6 n c 2 v s s 3 5 d 1 6 8 eo p / tc 2 10 1 xint 4 13 4 a1 9 16 7 de n 3 d2 3 3 6 d 0 6 9 eo p / tc 3 10 2 xint 5 13 5 v s s 16 8 v c c 4 d2 2 3 7 v c c 7 0 v s s 10 3 v c c 13 6 a2 0 16 9 blas t 5 d2 1 3 8 v s s 7 1 v c c 10 4 n c 13 7 a2 1 17 0 be 0 6 d2 0 3 9 v s s 7 2 v ccpl l 10 5 v s s 13 8 a2 2 17 1 v c c 7 v s s 4 0 bof f 7 3 n c 10 6 xint 6 13 9 a2 3 17 2 be 1 8 d1 9 4 1 n c 7 4 pclk 2 10 7 xint 7 14 0 v c c 17 3 v s s 9 d1 8 4 2 n c 7 5 v s s 10 8 nm i 14 1 a2 4 17 4 v s s 1 0 d1 7 4 3 onc e 7 6 n c 10 9 v s s 14 2 a2 5 17 5 be 2 1 1 d1 6 4 4 v c c 7 7 v s s 11 0 v s s 14 3 a2 6 17 6 be 3 1 2 v c c 4 5 fai l 7 8 pclk 1 11 1 a 2 14 4 a2 7 17 7 n c 1 3 d1 5 4 6 stes t 7 9 v c c 11 2 a 3 14 5 a2 8 17 8 ad s 1 4 d1 4 4 7 n c 8 0 n c 11 3 a 4 14 6 n c 17 9 hold a 1 5 d1 3 4 8 n c 8 1 v s s 11 4 a 5 14 7 v s s 18 0 v c c 1 6 v s s 4 9 v s s 8 2 v c c 11 5 v c c 14 8 v c c 18 1 hol d 1 7 d1 2 5 0 v c c 8 3 v s s 11 6 a 6 14 9 n c 18 2 read y 1 8 d1 1 5 1 n c 8 4 n c 11 7 a 7 15 0 v s s 18 3 n c 1 9 d1 0 5 2 n c 8 5 clkmod e 11 8 a 8 15 1 a2 9 18 4 bter m 2 0 v c c 5 3 n c 8 6 n c 11 9 a 9 15 2 a3 0 18 5 v s s 2 1 d 9 5 4 n c 8 7 clki n 12 0 a1 0 15 3 a3 1 18 6 d3 1 2 2 d 8 5 5 n c 8 8 v s s 12 1 v s s 15 4 v c c 18 7 d3 0 2 3 d 7 5 6 v s s 8 9 v s s 12 2 a1 1 15 5 bre q 18 8 d2 9 2 4 v s s 5 7 dreq 0 9 0 n c 12 3 a1 2 15 6 loc k 18 9 d2 8 2 5 d 6 5 8 dreq 1 9 1 rese t 12 4 a1 3 15 7 n c 19 0 v c c 2 6 d 5 5 9 dreq 2 9 2 v s s 12 5 v s s 15 8 su p 19 1 d2 7 2 7 d 4 6 0 dreq 3 9 3 xint 0 12 6 n c 15 9 d / c 19 2 d2 6 2 8 v c c 6 1 v c c 9 4 xint 1 12 7 v c c 16 0 dm a 19 3 n c 2 9 n c 6 2 dack 0 9 5 xint 2 12 8 a1 4 16 1 v s s 19 4 d2 5 3 0 v s s 6 3 dack 1 9 6 v c c 12 9 a1 5 16 2 wai t 19 5 d2 4 3 1 n c 6 4 dack 2 9 7 n c 13 0 a1 6 16 3 dt / r 19 6 v s s 3 2 v c c 6 5 dack 3 9 8 v s s 13 1 v s s 16 4 w / r 3 3 d 3 6 6 eo p / tc 0 9 9 v c c 13 2 a1 7 16 5 v s s
1 7 80960ca-33, -25, -1 6 figure 4. 80960 c a pqfp pinout (view from top side ) 50 98 99 147 148 196 pin 1 49 f_ca004a
1 8 80960ca-33, -25, -1 6 3.4 package thermal specification s the 80960 c a is specified for operation when t c (case temperature) is within the range of 0 o c?10 0 o c. t c may be measured in any environment to dete r - mine whether the 80960 c a is within specified ope r - ating range. case temperature should be measured at the center of the top surface, opposite the pins. refer to figure 5 . t a (ambient temperature) can be calculated from q ca (thermal resistance from case to ambient) using the following equation : t a = t c ? p * q c a table 1 0 shows the maximum t a allowable (without exceeding t c ) at various airflows and operating frequencies ( f pcl k ) . note that t a is greatly improved by attaching fins or a heatsink to the package. p (maximum power consumption) is calculated by using the typical i cc as tabulated in section 4.4, dc specification s and v c c of 5v . figure 5. measuring 80960 c a pga and pqfp case temperatur e table 10. maximum t a at various airflows in o c (pga package only ) airflow-ft/min (m/sec ) f pcl k (mhz ) 0 (0 ) 20 0 (1.01 ) 40 0 (2.03 ) 60 0 (3.04 ) 80 0 (4.06 ) 100 0 (5.07 ) t a with heatsink * 3 3 2 5 1 6 5 1 6 1 7 4 6 6 7 3 8 2 7 9 8 3 8 9 8 1 8 5 9 0 8 5 8 8 9 2 8 7 8 9 9 3 t a without heatsink * 3 3 2 5 1 6 3 6 4 9 6 6 4 7 5 8 7 2 5 9 6 7 7 8 6 6 7 3 8 2 7 3 7 8 8 6 7 5 8 0 8 7 notes : *0.285? high unidirectional heatsink (ai alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing) . measure pqfp case temperature at center of top surface. measure pga temperature at center of top surface 168 - pin pga pin 196 pin 1 f_cx007a
1 9 80960ca-33, -25, -1 6 table 11. 80960 c a pga package thermal characteristic s thermal resistance ? c/wat t paramete r airflow ? ft./min (m/sec ) 0 (0 ) 20 0 (1.01 ) 40 0 (2.03 ) 60 0 (3.07 ) 80 0 (4.06 ) 100 0 (5.07 ) q junction-to-case (case measured as shown in figure 5 ) 1. 5 1. 5 1. 5 1. 5 1. 5 1. 5 q case-to-ambient (no heatsink ) 1 7 1 4 1 1 9 7. 1 6. 6 q case-to-ambient (with heatsink) * 1 3 9 5. 5 5 3. 9 3. 4 notes : 1. this table applies to 80960ca pga plugged into socket or soldered directly to board . 2. q j a = q j c + q c a *0.285? high unidirectional heatsink (ai alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing) . table 12. 80960 c a pqfp package thermal characteristic s thermal resistance ? c/wat t paramete r airflow ? ft./min (m/sec ) 0 (0 ) 5 0 (0.25 ) 10 0 (0.50 ) 20 0 (1.01 ) 40 0 (2.03 ) 60 0 (3.04 ) 80 0 (4.06 ) q junction-to-case (case measured as shown in figure 5 ) 5 5 5 5 5 5 5 q case-to-ambient (no heatsink ) 1 9 1 8 1 7 1 5 1 2 1 0 9 notes : 1. this table applies to 80960ca pqfp soldered directly to board . 2. q j a = q j c + q c a q jc q ja q jc
2 0 80960ca-33, -25, -1 6 3.5 stepping register informatio n upon reset, register g0 contains die stepping info r - mation. figure 6 shows how g0 is configured. the most significant byte contains an ascii 0. the upper middle byte contains an ascii c. the lower middle byte contains an ascii a . the least significant byte contains the stepping number in ascii. g0 retains this information until it is overwritten by the user program . figure 6. register g 0 table 1 3 contains a cross reference of the number in the least significant byte of register g0 to the die stepping number . table 13. die stepping cross referenc e g0 least significant byt e die steppin g 0 1 b 0 2 c- 1 0 3 c-2,c- 3 0 4 d ascii 0 0 4 3 4 1 stepping numbe r decimal 0 c a stepping numbe r ms b ls b 3.6 suggested sources for 80960 c a accessorie s the following is a list of suggested sources for 80960 c a accessories. this is not an endorsement of any kind, nor is it a warranty of the performance of any of the listed products and/or companies . socket s 1. 3m textool test and interconnection products department p.o. box 2963 austin, tx 78769-296 3 2. augat, inc. interconnection products group 33 perry avenue p.o. box 779 attleboro, ma 02703 (508) 699-764 6 3. concept manufacturing, inc. (decoupling sockets) 41484 christy street fremont, ca 94538 (415) 651-380 4 heatsinks/fin s 1. thermalloy, inc. 2021 west valley view lane dallas, tx 75234-8993 (214) 243-4321 fax: (214) 241-465 6 2. e g & g division 60 audubon road wakefield, ma 01880 (617) 245-590 0
2 1 80960ca-33, -25, -1 6 4.0 electrical specification s 4.1 absolute maximum rating s paramete r maximum ratin g storage temperature ................................ ?6 5 o c to +15 0 o c case temperature under bias ................. ?6 5 o c to +11 0 o c supply voltage wrt. v ss ............................. ?0.5v to + 6.5 v voltage on other pins wrt. v ss ........... ?0.5v to v c c + 0.5 v notice : this is a production data sheet. the specifications are subject to change without notice . *warning : stressing the device beyond the ?absolute maximum ratings? may cause perm a - nent damage. these are stress ratings only. oper a - tion beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability . 4.2 operating condition s table 14. operating conditions (80960 c a -33, -25, -16 ) symbo l paramete r mi n ma x unit s note s v c c supply voltage 80960 c a -33 80960 c a -25 80960 c a -1 6 4.75 4.50 4.5 0 5.25 5.50 5.5 0 v v v f clk2 x input clock frequency (2-x mode) 80960 c a -33 80960 c a -25 80960 c a -1 6 0 0 0 66.66 50 3 2 mhz mhz mh z f clk1 x input clock frequency (1-x mode) 80960 c a -33 80960 c a -25 80960 c a -1 6 8 8 8 33.33 25 1 6 mhz mhz mh z (1 ) t c case temperature under bias pga package 80960 c a -33, -25, -16 196-pin pqf p 0 0 100 10 0 o c o c notes : 1. when in the 1-x input clock mode, clkin is an input to an internal phase-locked loop and must maintain a minimum fr e - quency of 8 mhz for proper processor operation. however, in the 1-x mode, clkin may still be stopped when the pr o - cessor either is in a reset condition or is reset. if clkin is stopped, the specified rese t low time must be provided once clkin restarts and has stabilized . 4.3 recommended connection s power and ground connections must be made to multiple v c c and v s s (gnd) pins. every 80960 c a - based circuit board should include power ( v c c ) and ground ( v s s ) planes for power distribution. every v c c pin must be connected to the power plane, and every v s s pin must be connected to the ground plane. pins identified as ?nc? must no t be connected in the system . liberal decoupling capacitance should be placed near the 80960 c a . the processor can cause tra n - sient power surges when its numerous output buffers transition, particularly when connected to large capacitive loads . low inductance capacitors and interconnects are recommended for best high frequency electrical performance. inductance can be reduced by shor t - ening the board traces between the processor and decoupling capacitors as much as possible. capac i - tors specifically designed for pga packages will offer the lowest possible inductance . for reliable operation, always connect unused inputs to an appropriate signal level. in particular, any unused interrupt ( xin t , nm i ) or dma ( dre q ) input should be connected to v c c through a pull-up resistor, as should bter m if not used. pull-up resi s - tors should be in the in the range of 2 0 k w for each pin tied high. if read y or hold are not used, the unused input should be connected to ground . n.c. pins must always remain unconnected. refer to the i96 0 cx microprocessor user?s manua l (order number 270710) for more information .
2 2 80960ca-33, -25, -1 6 4.4 dc specification s table 15. dc characteristic s (80960 c a -33, -25, -16 under the conditions described in section 4.2, operating condition s . ) symbo l paramete r mi n ma x unit s note s v i l input lo w voltage for all pins except rese t ? 0. 3 +0. 8 v v i h input high voltage for all pins except rese t 2. 0 v c c + 0. 3 v v o l output low voltag e 0.4 5 v i o l = 5 m a v o h output high voltage i o h = ?1 ma i o h = ? 20 0 m a 2.4 v c c ? 0. 5 v v v il r input low voltage for rese t ? 0. 3 1. 5 v v ih r input high voltage for rese t 3. 5 v c c + 0. 3 v i li 1 input leakage current for each pin excep t : bter m , onc e , dreq3: 0 , stest, eop3: 0 / tc3: 0 , nm i , xint7: 0 , bof f , read y , hold, clkmod e 1 5 a 0 v i n v c c (1 ) i li 2 input leakage current for: bter m , onc e , dreq3: 0 , stest, eop3: 0 / tc3: 0 , nm i , xint7: 0 , bof f 0 ? 30 0 a v i n = 0.45 v (2 ) i li 3 input leakage current for: read y , hold, clkmod e 0 50 0 a v i n = 2.4v (3,7 ) i l o output leakage curren t 1 5 a 0.45 v ou t v c c i c c supply current (80960 c a -33): i c c max i c c ty p 90 0 75 0 ma m a (4) (5 ) i c c supply current (80960 c a -25): i c c max i c c ty p 75 0 60 0 ma m a (4) (5 ) i c c supply current (80960 c a -16): i c c max i c c ty p 55 0 40 0 ma m a (4) (5 ) i onc e once-mode supply curren t 10 0 m a c i n input capacitance for: clkin, rese t , onc e , read y , hold, dreq3: 0 , bof f , xint7: 0 , nm i , bter m , clkmod e 0 1 2 p f f c = 1 mhz c ou t output capacitance of each output pi n 1 2 p f f c = 1 mhz (6 ) c i/ o i/o pin capacitanc e 1 2 p f f c = 1 mhz notes : 1. no pullup or pulldown . 2. these pins have internal pullup resistors . 3. these pins have internal pulldown resistors . 4. measured at worst case frequency, v c c and temperature, with device operating and outputs loaded to the test conditions described in se c - tion 4.5.1, ac test condition s . 5. i c c typical is not tested . 6. output capacitance is the capacitive load of a floating output . 7. clkmode pin has a pulldown resistor only when onc e pin is deasserted .
2 3 80960ca-33, -25, -1 6 4.5 ac specification s table 16. 80960 c a ac characteristics (33 mhz) (80960 c a -33 only, under the conditions described in section 4.2, operating condition s and section 4.5.1, ac test condition s . ) symbo l paramete r mi n ma x unit s note s input cloc k (1,9 ) t f clkin frequenc y 0 66.6 6 mh z t c clkin period in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) 30 1 5 125 ns n s (11 ) t c s clkin period stability in 1-x mode (f clk1 x ) 0.1 % d (12 ) t c h clkin high time in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) 6 6 62.5 ns n s (11 ) t c l clkin low time in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) 6 6 62.5 ns n s (11 ) t c r clkin rise tim e 0 6 n s t c f clkin fall tim e 0 6 n s output clock s (1,8 ) t c p clkin to pclk2:1 delay in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) ? 2 2 2 2 5 ns n s (3,12) (3 ) t pclk2:1 period in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) t c 2 t c ns n s (12) (3 ) t p h pclk2:1 high tim e (t/2) ? 2 t/ 2 n s (12 ) t p l pclk2:1 low tim e (t/2) ? 2 t/ 2 n s (12 ) t p r pclk2:1 rise tim e 1 4 n s (3 ) t p f pclk2:1 fall tim e 1 4 n s (3 ) synchronous output s (8 ) t oh t o v output valid delay, output hold t oh 1 , t ov1 a31:2 t oh 2 , t ov2 be3:0 t oh 3 , t ov3 ads t oh 4 , t ov4 w / r t oh 5 , t ov5 d / c , su p , dma t oh 6 , t ov6 blas t , wait t oh 7 , t ov7 den t oh 8 , t ov8 holda, breq t oh 9 , t ov9 lock t oh1 0 , t ov10 dack3:0 t oh1 1 , t ov11 d31:0 t oh1 2 , t ov12 dt / r t oh1 3 , t ov13 fail t oh1 4 , t ov14 eop3: 0 / tc3: 0 3 3 6 3 4 5 3 4 4 4 3 t/2 + 3 2 3 14 16 18 18 16 16 16 16 16 18 16 t/2 + 14 14 1 8 ns ns ns ns ns ns ns ns ns ns ns ns ns n s (6,10) (6,10 ) t o f output float for all output s 3 2 2 n s (6 ) synchronous input s (1,9,10 ) t i s input setup t is 1 d31:0 t is 2 boff t is 3 bter m / ready t is 4 hol d 3 17 7 7 ns ns ns n s t i h input hold t ih 1 d31:0 t ih 2 boff t ih 3 bter m / ready t ih 4 hol d 5 5 2 3 ns ns ns n s
2 4 80960ca-33, -25, -1 6 relative output timing s (1,2,3,8 ) t avsh 1 a31:2 valid to ad s risin g t ? 4 t + 4 n s t avsh 2 be3: 0 , w / r , su p , d / c , dm a , dack3: 0 valid to ad s risin g t ? 6 t + 6 n s t avel 1 a31:2 valid to de n fallin g t ? 4 t + 4 n s t avel 2 be3: 0 , w / r , su p , ins t , dm a , dack3: 0 valid to de n fallin g t ? 6 t + 6 n s t nlq v wai t falling to output data vali d 4 n s t dvn h output data valid to wai t risin g n*t ? 4 n*t + 4 n s (4 ) t nln h wai t falling to wai t risin g n*t 4 n s (4 ) t nhq x output data hold after wai t risin g (n+1)*t? 8 (n+1)*t+ 6 n s (5 ) t eht v dt / r hold after de n hig h t/2 ? 7 n s (6 ) t tve l dt / r valid to de n fallin g t/2 ? 4 n s relative input timings (1,2,3 ) t is 5 rese t input setup (2-x clock mode ) 6 n s (13 ) t ih 5 rese t input hold (2-x clock mode ) 5 n s (13 ) t is 6 dreq3: 0 input setu p 1 2 n s (7 ) t ih 6 dreq3: 0 input hol d 7 n s (7 ) t is 7 xint7: 0 , nm i input setu p 7 n s (15 ) t ih 7 xint7: 0 , nm i input hol d 3 n s (15 ) t is 8 rese t input setup (1-x clock mode ) 3 n s (14 ) t ih 8 rese t input hold (1-x clock mode ) t/4 + 1 n s (14 ) notes : 1. see section 4.5.2, ac timing waveform s for waveforms and definitions . 2. see figure 1 6 for capacitive derating information for output delays and hold times . 3. see figure 1 7 for capacitive derating information for rise and fall times . 4. where n is the number of n ra d , n rd d , n wa d or n wd d wait states that are programmed in the bus controller region table. wai t never goes active when there are no wait states in an access . 5. n = number of wait states inserted with read y . 6. output data and/or dt / r may be driven indefinitely following a cycle if there is no subsequent bus activity . 7. since asynchronous inputs are synchronized internally by the 80960 c a , they have no required setup or hold times to be recognized and for proper operation. however, to guarantee recognition of the input at a particular edge of pclk2:1, the setup times shown must be met. asy n - chronous inputs must be active for at least two consecutive pclk2:1 rising edges to be seen by the processor . 8. these specifications are guaranteed by the processor . 9. these specifications must be met by the system for proper operation of the processor . 10. this timing is dependent upon the loading of pclk2:1. use the derating curves of section 4.5.3, derating curve s to adjust the timing for pclk2:1 loading . 11. in the 1-x input clock mode, the maximum input clock period is limited to 12 5 ns while the processor is operating. when the processor is in reset, the input clock may stop even in 1-x mode . 12. when in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than 0.1% b etween adj a - cent cycles . 13. in 2-x clock mode, rese t is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the rese t pin must meet setup and hold times to the falling edge of the clkin. (see figure 2 2 . ) 14. in 1-x clock mode, rese t is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the rese t pin must meet setup and hold times to the rising edge of the clkin. (see figure 2 3 . ) 15. the interrupt pins are synchronized internally by the 80960 c a . they have no required setup or hold times for proper operation. these pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive pclk2:1 rising edges when asser t - ing them asynchronously. to guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consec u - tive pclk2:1 rising edges . table 16. 80960 c a ac characteristics (33 mhz) (continued ) (80960 c a -33 only, under the conditions described in section 4.2, operating condition s and section 4.5.1, ac test condition s . ) symbo l paramete r mi n ma x unit s note s
2 5 80960ca-33, -25, -1 6 table 17. 80960 c a ac characteristics (25 mhz) (80960 c a -25 only, under conditions described in section 4.2, operating condition s and section 4.5.1, ac test condition s . ) symbo l paramete r mi n ma x unit s note s input cloc k (1,9 ) t f clkin frequenc y 0 5 0 mh z t c clkin period in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) 40 2 0 125 ns n s (11 ) t c s clkin period stability in 1-x mode (f clk1 x ) 0.1 % d (12 ) t c h clkin high time in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) 8 8 62.5 ns n s (11 ) t c l clkin low time in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) 8 8 62.5 ns n s (11 ) t c r clkin rise tim e 0 6 n s t c f clkin fall tim e 0 6 n s output clock s (1,8 ) t c p clkin to pclk2:1 delay in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) ? 2 2 2 2 5 ns n s (3,12) (3 ) t pclk2:1 period in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) t c 2 t c ns n s (12) (3 ) t p h pclk2:1 high tim e (t/2) ? 3 t/ 2 n s (12 ) t p l pclk2:1 low tim e (t/2) ? 3 t/ 2 n s (12 ) t p r pclk2:1 rise tim e 1 4 n s (3 ) t p f pclk2:1 fall tim e 1 4 n s (3 ) synchronous output s (8 ) t oh t o v output valid delay, output hold t oh 1 , t ov1 a31:2 t oh 2 , t ov2 be3:0 t oh 3 , t ov3 ads t oh 4 , t ov4 w / r t oh 5 , t ov5 d / c , su p , dma t oh 6 , t ov6 blas t , wait t oh 7 , t ov7 den t oh 8 , t ov8 holda, breq t oh 9 , t ov9 lock t oh1 0 , t ov10 dack3:0 t oh1 1 , t ov11 d31:0 t oh1 2 , t ov12 dt / r t oh1 3 , t ov13 fail t oh1 4 , t ov14 eop3: 0 / tc3: 0 3 3 6 3 4 5 3 4 4 4 3 t/2 + 3 2 3 16 18 20 20 18 18 18 18 18 20 18 t/2 + 16 16 2 0 ns ns ns ns ns ns ns ns ns ns ns ns ns n s (6,10) (6,10 ) t o f output float for all output s 3 2 2 n s (6 ) synchronous input s (1,9,10 ) t i s input setup t is 1 d31:0 t is 2 boff t is 3 bter m / ready t is 4 hol d 5 19 9 9 ns ns ns n s t i h input hold t ih 1 d31:0 t ih 2 boff t ih 3 bter m / ready t ih 4 hol d 5 7 2 5 ns ns ns n s
2 6 80960ca-33, -25, -1 6 relative output timing s (1,2,3,8 ) t avsh 1 a31:2 valid to ad s risin g t ? 4 t + 4 n s t avsh 2 be3: 0 , w / r , su p , d / c , dm a , dack3: 0 valid to ad s risin g t ? 6 t + 6 n s t avel 1 a31:2 valid to de n fallin g t ? 4 t + 4 n s t avel 2 be3: 0 , w / r , su p , ins t , dm a , dack3: 0 valid to de n fallin g t ? 6 t + 6 n s t nlq v wai t falling to output data vali d 4 n s t dvn h output data valid to wai t risin g n*t ? 4 n*t + 4 n s (4 ) t nln h wai t falling to wai t risin g n*t 4 n s (4 ) t nhq x output data hold after wai t risin g (n+1)*t? 8 (n+1)*t+ 6 n s (5 ) t eht v dt / r hold after de n hig h t/2 ? 7 n s (6 ) t tve l dt / r valid to de n fallin g t/2 ? 4 n s relative input timings (1,2,3 ) t is 5 rese t input setup (2-x clock mode ) 8 n s (13 ) t ih 5 rese t input hold (2-x clock mode ) 7 n s (13 ) t is 6 dreq3: 0 input setu p 1 4 n s (7 ) t ih 6 dreq3: 0 input hol d 9 n s (7 ) t is 7 xint7: 0 , nm i input setu p 9 n s (15 ) t ih 7 xint7: 0 , nm i input hol d 5 n s (15 ) t is 8 rese t input setup (1-x clock mode ) 3 n s (14 ) t ih 8 rese t input hold (1-x clock mode ) t/4 + 1 n s (14 ) notes : 1. see section 4.5.2, ac timing waveform s for waveforms and definitions . 2. see figure 1 6 for capacitive derating information for output delays and hold times . 3. see figure 1 7 for capacitive derating information for rise and fall times . 4. where n is the number of n ra d , n rd d , n wa d or n wd d wait states that are programmed in the bus controller region table . wai t never goes active when there are no wait states in an access . 5. n = number of wait states inserted with read y . 6. output data and/or dt / r may be driven indefinitely following a cycle if there is no subsequent bus activity . 7. since asynchronous inputs are synchronized internally by the 80960 c a , they have no required setup or hold times to be recognized and for proper operation. however, to guarantee recognition of the input at a particular edge of pclk2:1, the setup times shown must be met. asy n - chronous inputs must be active for at least two consecutive pclk2:1 rising edges to be seen by the processor . 8. these specifications are guaranteed by the processor . 9. these specifications must be met by the system for proper operation of the processor . 10. this timing is dependent upon the loading of pclk2:1. use the derating curves of section 4.5.3, derating curve s to adjust the timing for pclk2:1 loading . 11. in the 1-x input clock mode, the maximum input clock period is limited to 12 5 ns while the processor is operating. when the processor is in reset, the input clock may stop even in 1-x mode . 12. when in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than 0.1% b etween adj a - cent cycles . 13. in 2-x clock mode, rese t is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the rese t pin must meet setup and hold times to the falling edge of the clkin. (see figure 2 2 . ) 14. in 1-x clock mode, rese t is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the rese t pin must meet setup and hold times to the rising edge of the clkin. (see figure 2 3 . ) 15. the interrupt pins are synchronized internally by the 80960 c a . they have no required setup or hold times for proper operation. these pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive pclk2:1 rising edges when asser t - ing them asynchronously. to guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consec u - tive pclk2:1 rising edges . table 17. 80960 c a ac characteristics (25 mhz) (continued ) (80960 c a -25 only, under conditions described in section 4.2, operating condition s and section 4.5.1, ac test condition s . ) symbo l paramete r mi n ma x unit s note s
2 7 80960ca-33, -25, -1 6 table 18. 80960 c a ac characteristics (16 mhz) (80960 c a -16 only, under conditions described in section 4.2, operating condition s and section 4.5.1, ac test condition s . ) symbo l paramete r mi n ma x unit s note s input cloc k (1,9 ) t f clkin frequenc y 0 3 2 mh z t c clkin period in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) 62.5 31.2 5 125 ns n s (11 ) t c s clkin period stability in 1-x mode (f clk1 x ) 0.1 % d (12 ) t c h clkin high time in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) 10 1 0 62.5 ns n s (11 ) t c l clkin low time in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) 10 1 0 62.5 ns n s (11 ) t c r clkin rise tim e 0 6 n s t c f clkin fall tim e 0 6 n s output clock s (1,8 ) t c p clkin to pclk2:1 delay in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) ? 2 2 2 2 5 ns n s (3,12) (3 ) t pclk2:1 period in 1-x mode (f clk1 x ) in 2-x mode (f clk2 x ) t c 2 t c ns n s (12) (3 ) t p h pclk2:1 high tim e (t/2) ? 4 t/ 2 n s (12 ) t p l pclk2:1 low tim e (t/2) ? 4 t/ 2 n s (12 ) t p r pclk2:1 rise tim e 1 4 n s (3 ) t p f pclk2:1 fall tim e 1 4 n s (3 ) synchronous output s (8 ) t oh t o v output valid delay, output hold t oh 1 , t ov1 a31:2 t oh 2 , t ov2 be3:0 t oh 3 , t ov3 ads t oh 4 , t ov4 w / r t oh 5 , t ov5 d / c , su p , dma t oh 6 , t ov6 blas t , wait t oh 7 , t ov7 den t oh 8 , t ov8 holda, breq t oh 9 , t ov9 lock t oh1 0 , t ov10 dack3:0 t oh1 1 , t ov11 d31:0 t oh1 2 , t ov12 dt / r t oh1 3 , t ov13 fail t oh1 4 , t ov14 eop3: 0 / tc3: 0 3 3 6 3 4 5 3 4 4 4 3 t/2 + 3 2 3 18 20 22 22 20 20 20 20 20 22 20 t/2 + 18 18 2 2 ns ns ns ns ns ns ns ns ns ns ns ns ns n s (6,10) (6,10 ) t o f output float for all output s 3 2 2 n s (6 ) synchronous input s (1,9,10 ) t i s input setup t is 1 d31:0 t is 2 boff t is 3 bter m / ready t is 4 hol d 5 21 9 9 ns ns ns n s t i h input hold t ih 1 d31:0 t ih 2 boff t ih 3 bter m / ready t ih 4 hol d 5 7 2 5 ns ns ns n s
2 8 80960ca-33, -25, -1 6 relative output timing s (1,2,3,8 ) t avsh 1 a31:2 valid to ad s risin g t ? 4 t + 4 n s t avsh 2 be3: 0 , w / r , su p , d / c , dm a , dack3: 0 valid to ad s risin g t ? 6 t + 6 n s t avel 1 a31:2 valid to de n fallin g t ? 6 t + 6 n s t avel 2 be3: 0 , w / r , su p , ins t , dm a , dack3: 0 valid to de n fallin g t ? 6 t + 6 n s t nlq v wai t falling to output data vali d 4 n s t dvn h output data valid to wai t risin g n*t ? 4 n*t + 4 n s (4 ) t nln h wai t falling to wai t risin g n*t 4 n s (4 ) t nhq x output data hold after wai t risin g (n+1)*t? 8 (n+1)*t+ 6 n s (5 ) t eht v dt / r hold after de n hig h t/2 ? 7 n s (6 ) t tve l dt / r valid to de n fallin g t/2 ? 4 n s relative input timings (1,2,3 ) t is 5 rese t input setup (2-x clock mode ) 1 0 n s (13 ) t ih 5 rese t input hold (2-x clock mode ) 9 n s (13 ) t is 6 dreq3: 0 input setu p 1 6 n s (7 ) t ih 6 dreq3: 0 input hol d 1 1 n s (7 ) t is 7 xint7: 0 , nm i input setu p 9 n s (15 ) t ih 7 xint7: 0 , nm i input hol d 5 n s (15 ) t is 8 rese t input setup (1-x clock mode ) 3 n s (14 ) t ih 8 rese t input hold (1-x clock mode ) t/4 + 1 n s (14 ) notes : 1. see section 4.5.2, ac timing waveform s for waveforms and definitions . 2. see figure 1 6 for capacitive derating information for output delays and hold times . 3. see figure 1 7 for capacitive derating information for rise and fall times . 4. where n is the number of n ra d , n rd d , n wa d or n wd d wait states that are programmed in the bus controller region table. wai t never goes active when there are no wait states in an access . 5. n = number of wait states inserted with read y . 6. output data and/or dt / r may be driven indefinitely following a cycle if there is no subsequent bus activity . 7. since asynchronous inputs are synchronized internally by the 80960 c a , they have no required setup or hold times to be recognized and for proper operation. however, to guarantee recognition of the input at a particular edge of pclk2:1, the setup times shown must be met. asy n - chronous inputs must be active for at least two consecutive pclk2:1 rising edges to be seen by the processor . 8. these specifications are guaranteed by the processor . 9. these specifications must be met by the system for proper operation of the processor . 10. this timing is dependent upon the loading of pclk2:1. use the derating curves of section 4.5.3, derating curve s to adjust the timing for pclk2:1 loading . 11. in the 1-x input clock mode, the maximum input clock period is limited to 12 5 ns while the processor is operating. when the processor is in reset, the input clock may stop even in 1-x mode . 12. when in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than 0.1% b etween adj a - cent cycles . 13. in 2-x clock mode, rese t is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the rese t pin must meet setup and hold times to the falling edge of the clkin. (see figure 2 2 . ) 14. in 1-x clock mode, rese t is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the rese t pin must meet setup and hold times to the rising edge of the clkin. (see figure 2 3 . ) 15. the interrupt pins are synchronized internally by the 80960 c a . they have no required setup or hold times for proper operation. these pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive pclk2:1 rising edges whe n asserting them asynchronously. to guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two con secutive pclk2:1 rising edges . table 18. 80960 c a ac characteristics (16 mhz) (continued ) (80960 c a -16 only, under conditions described in section 4.2, operating condition s and section 4.5.1, ac test condition s . ) symbo l paramete r mi n ma x unit s note s
2 9 80960ca-33, -25, -1 6 4.5.1 ac test condition s the ac specifications in sectio n 4. 5 are tested with the 50 pf load shown in figure 7 . figure 1 6 shows how timings vary with load capacitance . specifications are measured at the 1.5v crossing point, unless otherwise indicated. input waveforms are assumed to have a rise and fall time of 2 ns from 0.8v to 2.0v. see section 4.5.2, ac timing waveform s for ac spec definitions, test points and illustrations . figure 7. ac test loa d output pin c l = 50 pf for all signals c l f_cx008a 4.5.2 ac timing waveform s figure 8. input and output clocks wavefor m figure 9. clkin wavefor m pclk2:1 2.4v 1.5v 1.5v 1.5v 0.45v t cp t ph t pl t pr t pf t f_cx009a clkin 2.0v 1.5v 0.8v t cf t ch t cl t c t cr f_cx010a
3 0 80960ca-33, -25, -1 6 figure 10. output delay and float wavefor m figure 11. input setup and hold wavefor m pclk2:1 outputs 1.5v 1.5v t ov min max t oh min max t of 1.5v 1.5v 1.5v 1.5v outputs f_cx011a pclk2:1 inputs: 1.5v 1.5v 1.5v valid t is t ih ( read y , hold, bter m , bof f , dreq3: 0 , d31:0 on reads) f_cx012a min max t o v t o h - output delay - the maximum output delay is referred to as the output valid delay ( t o v ). the minimum output delay is referred to as the output hold ( t o h ). t o f - output float delay - the output float condition occurs when the maximum output current becomes less that i l o in magnitude. t i s t i h - input setup and hold - the input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation.
3 1 80960ca-33, -25, -1 6 figure 12. nm i , xint7: 0 input setup and hold wavefor m figure 13. hold acknowledge timing s pclk2:1 1.5v 1.5v 1.5v valid t is t ih nm i , xint7:0 min min f_cx013a 1.5v 1.5v pclk2:1 1.5v 1.5v 1.5v outputs: a31:2, d31:0 , be3: 0 , ad s , blas t , wai t , w / r , dt / r , de n , loc k , d / c , su p , dma min max min max valid 1.5v valid t of t ov hold t is t ih 1.5v 1.5v 1.5v t ih t is holda t ov min min min min t ov max min max min t o v t o h - output delay - the maximum output delay is referred to as the output valid delay ( t o v ). the minimum output delay is referred to as the output hold ( t o h ). t o f - output float delay - the output float condition occurs when the maximum output current becomes less that i l o in magnitude. t i s t i h - input setup and hold - the input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation. f_cx014a 1.5v 1.5v 1.5v
3 2 80960ca-33, -25, -1 6 figure 14. bus backoff ( bof f ) timing s pclk2:1 1.5v 1.5v 1.5v outputs: a31:2, d31:0 , be3: 0 , ad s , blas t , wai t , w / r , dt / r , de n , loc k , d / c , su p , dma min max min max valid 1.5v valid t of t ov boff t is t ih 1.5v 1.5v 1.5v t ih t is f_cx015a 1.5v 1.5v
3 3 80960ca-33, -25, -1 6 figure 15. relative timings waveform s 4.5.3 derating curve s figure 16. output delay or hold vs. load capacitanc e pclk2:1 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v t avsh t dvhn t nhqx t nlnh t avel t vel t ehtv t nlqv ads a31:2, be3: 0 , w / r , loc k , su p , d / c , dma d31:0 wait dt / r den d31:0 f_cx016a 1.5v in v ih v il out 50 100 150 c l (pf) nom + 10 nom + 5 nom all outputs except: loc k , eop3: 0 / tc3: 0 , fail f_cx017a dm a , su p , breq, dack3: 0 , not e : pclk load = 50pf o u t p u t v a l i d d e l a y s ( n s ) @ 1 . 5 v loc k , dm a , su p , breq, dack3: 0 , eop3: 0 / tc3: 0 , fail
3 4 80960ca-33, -25, -1 6 figure 17. rise and fall time derating at highest operating temperature and minimum v c c figure 18. i c c vs. frequency and temperatur e 50 100 150 t i m e ( n s ) c l (pf) 10 8 6 4 2 50 100 150 t i m e ( n s ) c l (pf) 10 8 6 4 2 a) all outputs except: loc k , dm a , su p , holda, breq dack3: 0 , eop3: 0 / tc3: 0 , fail b) loc k , dm a , su p , holda, breq, dack3: 0 , eop3: 0 / tc3: 0 , fail 0.8v to 2.0v 0.8v to 2.0v f_cx019a 900 0 0 33 t c = 100 c t c = 0 c f pcl k (mhz) i c c ( m a ) i c c - i c c under test conditions f_cx020a
3 5 80960ca-33, -25, -1 6 5.0 reset, backoff and hold acknowledg e table 1 9 lists the condition of each processor output pin while rese t is asserted (low) . table 19. reset condition s pin s state during rese t (holda inactive ) 1 a31: 2 floatin g d31: 0 floatin g be3: 0 driven high (inactive ) w / r driven low (read ) ad s driven high (inactive ) wai t driven high (inactive ) blas t driven low (active ) dt / r driven low (receive ) de n driven high (inactive ) loc k driven high (inactive ) bre q driven low (inactive ) d / c floatin g dm a floatin g su p floatin g fai l driven low (active ) dack3: 0 driven high (inactive ) eop3: 0 / tc3: 0 floating (set to input mode ) notes : 1. with regard to bus output pin state only, the hold acknowledge state takes precedence over the reset state. although asserting the rese t pin will internally reset the processor, the processor?s bus output pins will not enter the reset state if it has granted hold acknowledge to a previous hold request (holda is active). furthermore, the processor will grant new hold requests and enter the hold acknowledge state even while in reset. for example, if holda is inactive and the processor is in the reset state, then hold is asserted, the proce s - sor?s bus pins enter the hold acknowledge state and holda is granted. the processor will not be able to perform memory accesses until the hold request is removed, even if the rese t pin is brought high. this operation is provided to simplify boot-up synchroniz a - tion among multiple processors sharing the same bus . table 2 0 lists the condition of each processor output pin while holda is asserted (low) . table 20. hold acknowledge and backoff condition s pin s state during holda a31: 2 floatin g d31: 0 floatin g be3: 0 floatin g w / r floatin g ad s floatin g wai t floatin g blas t floatin g dt / r floatin g de n floatin g loc k floatin g bre q driven (high or low ) d / c floatin g dm a floatin g su p floatin g fai l driven high (inactive ) dack3: 0 driven high (inactive ) eop3: 0 / tc3: 0 driven (if output )
3 6 80960ca-33, -25, -1 6 6.0 bus waveform s figure 19. cold reset wavefor m c l k i n p c l k 2 : 1 a d s , w / r , d t / r , i n s t , s u p , d 3 1 : 0 , s t e s t r e s e t v c c - o n c e b l a s t l o c k , w a i t , d e n , d a c k 3 : 0 b r e q , f a i l d m a , a 3 1 : 2 , d / c , b e 3 : 0 e o p / t c 3 : 0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ i n v a l i d v a l i d ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ c l k i n a n d v c c s t a b l e t o r e s e t h i g h , 3 2 c l k i n p e r i o d s i n 2 x m o d e , p e r i o d s i n 1 x m o d e . ~ ~ i n p u t s t d e l a y 1 p c l k t s e t u p 1 p c l k t h o l d 1 p c l k ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ m i n i m u m 1 0 , 0 0 0 c l k i n f _ c x 0 2 1 a ~ ~ ~ ~ r e s e t h i g h t o f i r s t b u s a c t i v i t y , a p p r o x i m a t e l y 3 2 p c l k p e r i o d s . v c c a n d c l k i n s t a b l e t o o u t p u t s v a l i d , m a x i m u m 3 2 c l k i n p e r i o d s .
3 7 80960ca-33, -25, -1 6 figure 20. warm reset wavefor m t d e l a y 1 p c l k ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ m a x i m u m r e s e t l o w t o r e s e t s t a t e 4 p c l k p e r i o d s 1 p c l k ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ f _ c x 0 2 2 a p c l k 2 : 1 a d s , w / r , d t / r , s u p , d 3 1 : 0 , s t e s t r e s e t b l a s t l o c k , w a i t , d e n , d a c k 3 : 0 b r e q , f a i l d m a , a 3 1 : 2 , d / c , b e 3 : 0 e o p / t c 3 : 0 v a l i d ~ ~ ~ ~ t h o l d t s e t u p 1 p c l k r e s e t h i g h t o f i r s t b u s a c t i v i t y , a p p r o x i m a t e l y 3 2 p c l k p e r i o d s m i n i m u m r e s e t l o w t i m e 1 6 p c l k p e r i o d s ~ ~ ~ ~
3 8 80960ca-33, -25, -1 6 figure 21. entering the once stat e c l k i n p c l k 2 : 1 a d s , b e 3 : 0 , a 3 1 : 2 , r e s e t o n c e ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ v c c a n d c l k i n s t a b l e t o o u t p u t s v a l i d , m a x i m u m 3 2 c l k i n p e r i o d s . ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ c l k i n a n d v c c s t a b l e a n d r e s e t l o w a n d o n c e l o w t o r e s e t h i g h , m i n i m u m 3 2 c l k i n p e r i o d s i n 2 x m o d e , 1 0 , 0 0 0 c l k i n p e r i o d s i n 1 x m o d e . ~ ~ d 3 1 : 0 , l o c k , w a i t , b l a s t , w / r , d / c , d e n , d t / r , h o l d , h o l d a , d m a , e o p 3 : 0 / t c 3 : 0 , s t e s t , x i n t 7 : 0 , n m i , d a c k 3 : 0 , d r e q 3 : 0 r e a d y , b t e r m b l a s t , f a i l , s u p , b r e q , ~ ~ ~ ~ ~ ~ ~ ~ m a x i m u m 3 2 c l k i n p e r i o d s r e q u i r e d a f t e r o n c e m o d e e n t e r e d v c c ~ ~ ~ ~ ~ ~ ~ ~ f _ c x 0 2 3 a ~ ~ c l k i n m a y n o t f l o a t . i t m u s t b e d r i v e n h i g h o r l o w o r c o n t i n u e t o r u n
3 9 80960ca-33, -25, -1 6 figure 22. clock synchronization in the 2-x clock mod e figure 23. clock synchronization in the 1-x clock mod e clkin reset pclk2:1 (case 1) pclk2:1 (case 2) 1.5v t ih t is 1.5v 1.5v 1.5v 1.5v 1.5v t cp max min t cp max min t cp sync not e : case 1 and case 2 show two possible polarities of pclk2:1 min 1.5v 1.5v 1.5v 1.5v 1.5v 1.5v f_cx024a max clkin 1.5v 1.5v reset t ih t is 1.5v 2x clk not e : in 1x clock mode, the rese t pin is actually sampled on the falling edge of 2xclk. 2xclk is an internal signal generated by the pll and is not available on an external pin. therefore, rese t is specified relative to the rising edge of clkin. the rese t pin is sampled when pclk is high. f_cx025a
4 0 80960ca-33, -25, -1 6 figure 24. non-burst, non-pipelined requests without wait state s in ads a31:4, su p , dm a , d / c , be3: 0 , lock w / r blast d t / r den a3:2 wait d31:0 pclk a d a d a d in valid valid valid valid valid r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 0 00 x xx x xx 0 00000 x xx 0 00000 off 0 disabled 0 0 0..0 disabled 0 valid f_cx026a out function bit value
4 1 80960ca-33, -25, -1 6 figure 25. non-burst, non-pipelined read request with wait state s ads a31:2 , be3:0 dm a , d / c , su p , lock w / r blast d t / r den wait d31:0 pclk a 3 2 1 d 1 r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 1 01 x xx x xx x xxxxx x xx 3 00011 off 0 disabled 0 0 0..0 disabled 0 in function bit value valid valid a f_cx027a
4 2 80960ca-33, -25, -1 6 figure 26. non-burst, non-pipelined write request with wait state s ads a31:2, w / r blast d t / r den su p , dm a , wait d31:0 pclk a 3 2 1 d 1 r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 1 01 x xx x xx 3 00011 x xx x xxxxxx off 0 disabled 0 0 0..0 disabled 0 out a function bit value valid valid d / c , lock f_cx028a be3:0
4 3 80960ca-33, -25, -1 6 figure 27. burst, non-pipelined read request without wait states, 32-bit bu s in0 ads a31:4, sup, dm a , d / c , be3: 0 , lock w / r blast d t / r den a3:2 wait d31:0 pclk a d d d d a r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 0 00 32-bit 10 x xx x xxxxx 0 00 0 00000 off 0 enabled 1 0 0..0 disabled 0 f_cx029a function bit value in3 in2 in1 valid 00 01 10 11
4 4 80960ca-33, -25, -1 6 figure 28. burst, non-pipelined read request with wait states, 32-bit bu s ads a31:4, su p , dm a , d/c, be3: 0 , lock w / r blast d t / r den a3:2 wait d31:0 pclk r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 1 01 32-bit 10 x xx x xxxxx 1 01 2 00010 off 0 enabled 1 0 0..0 disabled 0 a 2 1 d 1 d 1 d 1 d 1 a in1 in2 in3 in0 valid 00 11 01 10 function bit value f_cx030a
4 5 80960ca-33, -25, -1 6 figure 29. burst, non-pipelined write request without wait states, 32-bit bu s r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 0 00 32-bit 10 0 00 0 00000 x xx x xxxxx off 0 enabled 1 0 0..0 disabled 0 ads a31:4, su p , dm a , d / c , be3: 0 , lock w / r blast d t / r den a3:2 wait d31:0 pclk a d d d d a function bit value 00 01 10 11 out0 valid out3 out2 out1 f_cx031a
4 6 80960ca-33, -25, -1 6 figure 30. burst, non-pipelined write request with wait states, 32-bit bu s ads a31:4, su p , dm a , d / c , be3: 0 , lock w / r blast d t / r den a3:2 wait d31:0 pclk r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 1 01 32-bit 10 1 01 2 00010 x xx x xxxxx off 0 enabled 1 0 0..0 disabled 0 a 2 1 d 1 d 1 d 1 d 1 a out0 valid 00 11 01 10 function bit value out1 out2 out3 f_cx032a
4 7 80960ca-33, -25, -1 6 figure 31. burst, non-pipelined read request with wait states, 16-bit bu s ads su p , dm a , w / r blast d t / r den a3:2 wait d31:0 pclk r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 1 01 16-bit 01 x xx x xxxxx 1 01 2 00010 off 0 enabled 1 0 0..0 disabled 0 a 2 1 d 1 d 1 d 1 d 1 a function bit value valid a3:2 = 00 or 10 a3:2 = 01 or 11 d15:0 a1=0 d15:0 a1=1 d15:0 a1=0 d15:0 a1=1 d / c , loc k , a31:4, be 3 / bhe, be 1 /a1 be 0 / ble f_cx033a
4 8 80960ca-33, -25, -1 6 figure 32. burst, non-pipelined read request with wait states, 8-bit bu s ads su p , dm a , w / r blast d t / r den a3:2 wait d31:0 pclk r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 1 01 8-bit 00 x xx x xxxxx 1 01 2 00010 off 0 enabled 1 0 0..0 disabled 0 a 2 1 d 1 d 1 d 1 d 1 a function bit value valid a3:2 = 00, 01, 10 or 11 d7:0 byte 0 d7:0 byte 1 d7:0 byte 2 d7:0 byte 3 d / c , loc k , a31:4 be 1 /a1, a1:0 = 00 a1:0 = 01 a1:0 = 10 a1:0 =11 be 0 /a0 f_cx034a
4 9 80960ca-33, -25, -1 6 figure 33. non-burst, pipelined read request without wait states, 32-bit bu s non-pipelined request concludes pipelined reads begin. pipelined reads conclude, non-pipelined requests begin. ads a31:4, su p , dm a , d / c , lock blast wait d31:0 pclk r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 x xx x xx x xx x xxxxx x xx 0 00000 on 1 disabled 0 0 0..0 x x function bit value in d in d' in d'' in d''' in d'''' a a' d a'' d' a''' d'' a'''' d''' d'''' valid valid valid valid valid invalid invalid d t / r den a3:2 be3:0 valid valid valid valid valid invalid w / r f_cx035a
5 0 80960ca-33, -25, -1 6 figure 34. non-burst, pipelined read request with wait states, 32-bit bu s non-pipelined request concludes pipelined reads begin. pipelined reads conclude, non-pipelined requests begin. ads a31:4, su p , dm a , d / c , w / r blast d t / r den a3:2 wait d31:0 pclk be3:0 a 1 a' d 1 d' r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 x xx x xx x xx x xxxxx x xx 1 00001 on 1 disabled 1 0 0..0 x x in d' invalid valid valid invalid in d lock valid valid invalid function bit value f_cx036a
5 1 80960ca-33, -25, -1 6 figure 35. burst, pipelined read request without wait states, 32-bit bu s pipelined reads conclude, non-pipelined requests begin ads a31:4, su p , dm a , d / c , be3: 0 , lock w / r blast d t / r den a3:2 wait d31:0 pclk non-pipelined request concludes, pipelined reads begin r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 x xx 32-bit 10 x xx x xxxxx 0 00 0 00000 on 1 enabled 1 0 0..0 disabled 0 a d d d a' d' d' valid valid in- valid valid 01 10 11 00 in d in d in d in d in d in d valid d function bit value in- valid in- valid f_cx037a
5 2 80960ca-33, -25, -1 6 figure 36. burst, pipelined read request with wait states, 32-bit bu s ads a31:4, su p , dm a , d / c , be3: 0 , lock w / r a3:2 d31:0 wait blast dt / r den pclk r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 x xx 32-bit 10 x xx x xxxxx 1 01 2 00010 on 1 enabled 1 0 0..0 disabled 0 function bit value in d in d in d in d in d' a 2 1 d 1 d 1 d 1 a' 2 1 valid d d' valid in- valid in- valid 00 01 10 11 valid in- valid non-pipelined request concludes, pipelined reads begin. pipelined reads conclude, non-pipelined requests begin. f_cx038a
5 3 80960ca-33, -25, -1 6 figure 37. burst, pipelined read request with wait states, 16-bit bu s ads a31:4, su p , dm a , d / c , be 0 / bl e , w / r a3:2 be 1 /a1 wait blast dt / r den pclk r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 x xx 16-bit 10 x xx x xxxxx 1 01 2 00010 on 1 enabled 1 0 0..0 disabled 0 function bit value d15:0 a1=0 d15:0 a1=1 d15:0 a1=0 d15:0 a1=1 d15:0 d' a 2 1 d 1 d 1 d 1 a' 2 1 d d' in- valid non-pipelined request concludes, pipelined reads begin. pipelined reads conclude, non-pipelined requests begin. a3:2 = 00 or 10 a3:2 = 01 or 11 valid in- valid valid in- valid be 3 / bhe, d31:0 f_cx040a lock valid valid in- valid
5 4 80960ca-33, -25, -1 6 figure 38. burst, pipelined read request with wait states, 8-bit bu s ads a31:4, su p , dm a , d / c , lock w / r a3:2 be 1 /a1, wait blast dt / r den pclk r e s e r v e d byte order bus width n wdd n wad n xda n rdd n rad pipe- lining external read y control burst r e s e r v e d 31-23 22 18-17 21 20-19 16-12 7-3 11-10 9-8 2 1 0 x x 0 0 x xx 8-bit 10 x xx x xxxxx 1 01 2 00010 on 1 enabled 1 0 0..0 disabled 0 function bit value d7:0 byte 0 d7:0 byte 1 d7:0 byte 2 d7:0 byte 3 d7:0 d' a 2 1 d 1 d 1 d 1 a' 2 1 d d' in- valid non-pipelined request concludes, pipelined reads begin. pipelined reads conclude, non-pipelined requests begin. valid in- valid be 0 /a0 d31:0 a3:2 = 00, 01, 10, or 11 valid in- valid a1:0 = 00 a1:0 = 01 a1:0 = 10 a1:0 = 11 valid valid in- valid f_cx039a
5 5 80960ca-33, -25, -1 6 figure 39. using external read y pclk ads a31:4, su p , dt / r den ready w / r dm a , ins t , blast bterm a3:2 wait d31:0 d / c , be3: 0 , lock d0 d1 d2 d3 d0 d1 d2 d3 00 01 10 11 00 01 10 11 valid valid quad-word read request n ra d = 0, n rd d = 0, n xd a = 0 ready enabled quad-word write request n wa d = 1, n wd d = 0, n wd a = 0 ready enabled f_cx041a
5 6 80960ca-33, -25, -1 6 figure 40. terminating a burst with bter m pclk ads a31:4, su p , dt / r den ready w / r dm a , ins t , blast bterm a3:2 wait d31:0 d / c , be3: 0 , lock d0 d1 d2 d3 valid quad-word write request n wa d = 0, n wd d = 0, n wda = 0 ready enabled 00 01 10 11 not e : read y adds memory access time to data transfers, whether or not the bus access is a burst access. bter m interrupts a bus access, whether or not the bus access has more data transfers pending. either the read y signal or the bter m signal will terminate a bus access if the signal is asserted during the last (or only) data transfer of the bus access. see note f_cx042a
5 7 80960ca-33, -25, -1 6 figure 41. bof f functional timin g ads blast ready boff a31:2, su p , d31:0, bof f may not be asserted bof f may not be asserted bof f may be asserted to suspend request begin request end request suspend request non-burst regenerate ads dm a , d / c , be3: 0 , wai t , de n , dt / r (writes) burst may change resume request burst ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ note : read y / bterm must be enabled; n ra d , n rd d , n wa d , n wd d = 0 ~ ~ ~ ~ f_cx043a
5 8 80960ca-33, -25, -1 6 figure 42. hold functional timin g word read request n ra d =1, n xd a =1 word read request n ra d =0, n xd a =0 hold state hold state pclk2:1 ads a31:2, su p , dm a , d / c , be3: 0 , wai t , de n , dt / r blast hold holda valid valid f_cx044a
5 9 80960ca-33, -25, -1 6 figure 43. dre q and dac k functional timin g figure 44. eo p functional timin g pclk2:1 ads ! ( blast & ready dackx (all modes) dreqx (case 1) dreqx (case 2) note: f_cx018a & ! wai t ) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ high to prevent next bus cycle high to prevent next bus cycle system clock start dma bus request end of dma bus request dma acknowledge dma request t is5 t ih5 t is5 t ih5 (see note) 1. case 1: dre q must deassert before dac k deasserts. applications are fly-by and some packing and unpacking modes in which loads are followed by loads or stores are followed by stores. 2. case 2: dre q must be deasserted by the second clock (rising edge) after dac k is driven high. applications are non fly-by transfers and adjacent load-stores or store-loads. 3. dack x is asserted for the duration of a dma bus request. the request may consist of multiple bus accesses (defined by ad s and blas t . refer t o i96 0 a cx microprocessor user?s manua l for ?access?, ?request? definitions. ~ ~ ~ ~ pclk2:1 eop f_cx045a ~ ~ ~ ~ ~ ~ not e : eo p has the same ac timing requirements as dre q to prevent unwanted dma requests. eo p is not edge held for a minimum of 2 clock cycles then deasserted within 15 clock cycles. triggered. eo p must be 15 clks max 2 clks min
6 0 80960ca-33, -25, -1 6 figure 45. terminal count functional timin g figure 46. fai l functional timin g not e : terminal count becomes active during the last bus request of a buffer transfer. if the last load/store bus request is executed as multiple bus accesses, the tc will be active for the entire bus request. refer to th e i96 0 ? cx microprocessor user?s manua l for further information. pclk2 dreq ads dack tc f_cx046a rese t fai l ~65,000 cycles 5 cycles 102 cycles (bus test) pass (internal self-test) pass ~ ~ ~ ~ ~ ~ ~ ~ fail fail f_cx047a
6 1 80960ca-33, -25, -1 6 figure 47. a summary of aligned and unaligned transfers for little endian region s 0 4 8 12 16 20 24 0 1 2 3 4 5 6 one double-word short-word load/store word load/store double-word load/store byte, byte requests short request (aligned) short request (aligned) byte, byte requests word request (aligned) byte, short, byte, requests short, short requests byte, short, byte requests byte offset word offset f_cx048a one double-word burst (aligned) byte, short, word, byte requests short, word, short requests byte, word, short, byte requests word, word requests request (aligned)
6 2 80960ca-33, -25, -1 6 figure 48. a summary of aligned and unaligned transfers for little endian regions (continued ) 0 4 8 12 16 20 24 0 1 2 3 4 5 6 triple-word load/store quad-word load/store word, word, word requests requests double- double- word, word, word, word requests byte offset word offset one three-word request (aligned) byte, short, word, word, byte requests short requests short, word, word, byte, word, word, short, byte requests word, word, word requests one four-word request (aligned) byte, short, word, word, word, byte requests short, word, word, word, short requests byte, word, word, word, short, byte requests f_cx049a requests word, word word, word, word,
6 3 80960ca-33, -25, -1 6 figure 49. idle bus operatio n pclk ads a31:4, su p , dm a , inst, d / c , be3:0 lock w / r blast dt / r den a3:2 wait d31:0 read y , bterm write request n wa d =2, n xd a = 0 ready disabled idle bus (not in hold acknowledge state) read request n wa d =2, n xd a = 0 ready disabled in out valid valid valid valid valid valid f_cx050a
6 4 80960ca-33, -25, -1 6 7.0 revision histor y this data sheet supersedes data sheet 270727-005. specification changes in the 80960ca data sheet are a result of design changes. the sections significantly changed since the previous revision are : sectio n last rev . descriptio n table 11. 80960ca pga package thermal characteristic s -00 5 removed references and notes pertaining to q j-ca p and q j-pin . table 12. 80960ca pqfp package thermal characteristic s -00 5 removed references and notes pertaining to q j l and q jb . 3.3 80960ca mechanical dat a -00 5 removed section containing information on package dimensions. moved section header to encompass pinout tables and diagrams . 3.7 suggested sources for 80960ca accessorie s -00 5 removed entire section containing information about 80960ca accessories . tables 1 6 , 1 7 an d 1 8 80960ca ac chara c - teristics (33-, 25- and 16mhz, respectively ) -00 5 t tve l maximum deleted . t nhq x and t eht v minimums changed : was: is : t nhq x (n+1)*t-6 (n+1)*t- 8 t eht v t/2 - 6 t/2 - 7 al l -00 5 all timing diagrams and waveforms have been redrawn to conform to consistent format. data sheet formatting has been changed to conform to corporate standards. specific formatting changes are not itemized in this revision history .

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